Potential issues in receiving LVDS protocol data from external module using HSMC Connectors

Hi

1. The pin mapping of TI Mezzanine and LVDS part of HSMC are different. I've attached the timing diagram of TI module LVDS output and the pin diagrams for both. So a custom PCB that performs proper mapping of clock and data lanes would make them compatible, right?

==> yes

Also, is Frame Clock required for receiving data into HSMC?

==> Frame Clock is required.

I didn't see it being used in the LVDS Rx fabric of Intel FPGA.

==> Frame clock is the naming for ADC. LVDS RX IP is a generic IP...expected that your frame clock is connected to the rx_inclock.

2. I don't have much control on the ADC samples output configuration, except from data rate, from the TI module. I should be able to receive the data from two lanes synchronously using Intel FPGA IP, or there are some potential problems?

==> it seems to me that you have 4 lanes of data (not 2 lanes)