Occasional Contributor
Occasional ContributorSorry, I can not post the whole kernel code here, too many lines. Here's some results that can be seen directly:
For 18.1 std, the following code are succefully pipelined with II=1, with no warning:
But for 18.1 Pro, a fmax warning is shown in report.html as can be seen here:
dependency is found on variable find_idle_ch_id here:
For this reason, a fmax=190MHz is generated for a10 device, while for s5 device the fmax is 220MHz.
For my understanding, a10 is more a advanced device than s5, and should run higher frequence than stratix-v.
New ContributorKeep in mind that S5 was the "top of the line" FPGA not so long ago. I think the reason for Pro version existence are different Gen10 devices with diffent metal routing and I/O columns in the middle of the die. Routing across I/O columns and around congested areas typically the main reasons for extra tPD and lower frequency in A10 vs S5.
