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sgr's avatar
sgr
Icon for New Contributor rankNew Contributor
3 years ago

PCIe Hard IP PCIe PCIe Link Up signal

Hi,

I want to use Arria 10 PCIe Hard IP as the root port for my design, is there any signal in the PCIe hard IP to get to know the PCIe Link Up is done because in some other vendors we will get one output signal named "user_lnk_up" signal that will identify that the PCIe Express core is linked up with a host device.

So is there any signal in Arria 10 PCIe Hard IP related to PCIe Link Up ? Please get me back as soon as possible.

1 Reply

  • skbeh's avatar
    skbeh
    Icon for Contributor rankContributor
    3 years ago

    Hi Sir


    For Arria 10, signal ltssmstate[4:0] is being used to indicate PCIe link up status.

    A successful PCIe link up is indicated by ltssmstate[4:0]=5'b01111 (a.k.a. L0 state).


    This information is documented in Arria 10 PCI Express User Guide at below link.

    See Table 31. Hard IP Status Signals on page 55.

    https://www.intel.com/content/www/us/en/docs/programmable/683724.html


    LTSSM state: The LTSSM state machine encoding defines the following states:

    • 00000: Detect.Quiet

    • 00001: Detect.Active

    • 00010: Polling.Active

    • 00011: Polling.Compliance

    • 00100: Polling.Configuration

    • 00101: Polling.Speed

    • 00110: config.Linkwidthstart

    • 00111: Config.Linkaccept

    • 01000: Config.Lanenumaccept

    • 01001: Config.Lanenumwait

    • 01010: Config.Complete

    • 01011: Config.Idle

    • 01100: Recovery.Rcvlock

    • 01101: Recovery.Rcvconfig

    • 01110: Recovery.Idle

    • 01111: L0

    • 10000: Disable

    • 10001: Loopback.Entry

    • 10010: Loopback.Active

    • 10011: Loopback.Exit

    • 10100: Hot.Reset

    • 10101: L0s

    • 11001: L2.transmit.Wake

    • 11010: Recovery.Speed

    • 11011: Recovery.Equalization, Phase 0

    • 11100: Recovery.Equalization, Phase 1

    • 11101: Recovery.Equalization, Phase 2

    • 11110: Recovery.Equalization, Phase 3

    • 11111: Recovery.Equalization, Done


    In addition, signal lane_act[3:0] indicates the number of lanes being configured during link training.

    The following encodings are defined:

    - 4’b0001: 1 lane

    - 4’b0010: 2 lanes

    - 4’b0100: 4 lanes

    - 4’b1000: 8 lanes