Output of a slave component using HLS

Hi all,

I'm new to FPGA design and HLS compiler. I tried developing a matrix slave component which needs to interact with an Avalon memory mapped master interface.

hls_avalon_slave_component
component void matrix_6x6 (float *input, int mode, float *output) {
	float cParam[6][6] = 
		{
		{1, 1, 1, 1, 1, 1},
		{1, 1, 1, 1, 1, 1},
		{1, 1, 1, 1, 1, 1},
		{1, 1, 1, 1, 1, 1},
		{1, 1, 1, 1, 1, 1},
		{1, 1, 1, 1, 1, 1},
		};
	float nParam[6][6]= 
	{
		{-0.3180, 0.5319, 3.9623, 0.0010, 0.0689, 0.0173},
		{-0.3203, -0.5453, 3.9833, -0.0005, -0.1027, 0.0303},
		{0.5932, 0.0012, 3.8879, -0.0021, 0.0202, -0.1327},
		{-0.0012, -0.0240, 0.0071, 0.2665, 3.8957, 0.3263},
		{0.0159, 0.0103, 0.0080, 0.3353, -1.7172, 2.7507},
		{-0.0187, 0.0115, 0.0152, 0.3322, -2.2704, -3.0780},
	};
	float inputData[6];
	float resultBuffer[6];
	float sum = 0.0f;
		
	
		#pragma unroll
		for (int j=0; j<6; j++){
			for (int k=0; k<6; k++){
				if (mode == 0) {
					sum  = sum + (input[j] * cParam[k][j]);
				} else if (mode == 1) {
					sum  = sum + (input[j] * nParam[k][j]);
				} else {
					sum  = sum + (input[j] * cParam[k][j]);
				}
			}
		
			resultBuffer[j] = sum;
			sum = 0.0f;
		}	
	
	//output = input*params
	
	#pragma unroll
	for (int row=0; row<6; row++) {
		output[row] = resultBuffer[row];
	}			
}

On generating the verilog output, I got the following interface to be used in the top level module.

matrix_6x6 matrix_6x6_inst (
  // Interface: clock (clock end)
  .clock               ( ), // 1-bit clk input
  // Interface: reset (reset end)
  .resetn              ( ), // 1-bit reset_n input
  // Interface: irq (interrupt end)
  .done_irq            ( ), // 1-bit irq output
  // Interface: input0 (conduit sink)
  .input0              ( ), // 64-bit data input
  // Interface: mode (conduit sink)
  .mode                ( ), // 32-bit data input
  // Interface: output0 (conduit sink)
  .output0             ( ), // 64-bit data input
  // Interface: avmm_0_rw (avalon start)
  .avmm_0_rw_address   ( ), // 64-bit address output
  .avmm_0_rw_byteenable( ), // 8-bit byteenable output
  .avmm_0_rw_read      ( ), // 1-bit read output
  .avmm_0_rw_readdata  ( ), // 64-bit readdata input
  .avmm_0_rw_write     ( ), // 1-bit write output
  .avmm_0_rw_writedata ( ), // 64-bit writedata output
  // Interface: avs_cra (avalon end)
  .avs_cra_read        ( ), // 1-bit read input
  .avs_cra_write       ( ), // 1-bit write input
  .avs_cra_address     ( ), // 2-bit address input
  .avs_cra_writedata   ( ), // 64-bit writedata input
  .avs_cra_byteenable  ( ), // 8-bit byteenable input
  .avs_cra_readdata    ( )  // 64-bit readdata output
);

I want to access the output memory location for which I did *output in the HLS code. But, in the interface, it was generated as input.

Am I missing something here?

Kindly clarify,

Nivetha