OpenCL to RTL module interface timing?

Hi,

For your first question, the upstream module is responsible for sending the ivalid signal to the RTL component. The number of cycles that ivalid is high for depends on how long the RTL component keeps oready low. See page 159 of the 19.3 OpenCL programming guide for more details. The behaviour will also depend on whether the RTL component is stall-free.

For the second question, if the RTL component is stall-free, the output data will be available N cycles after receiving the input data where EXPECTED_LATENCY = N. For examples if N = 10 and the input arrives during the cycle #1, then the output will be available in cycle #11. The input arriving in cycle #2 will have an output available in cycle #12 and so forth. If the RTL component isn’t stall-free, then there’s no guarantee on what the number of cycles will be before getting the output. It’s reliant on the stall signals (ivalid, ovalid, iready, oready) in addition to the input data. Again, pae 159 of the 19.3 OpenCL programming guide describes the handshaking protocol for stallable RTL components.

Thanks