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Christoph9's avatar
Christoph9
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3 years ago

Non-Ordered Pipes for Random-Number-Generation

Hello, I currently am trying to fit a design onto the Arria10 FPGA that requires random-numbers at multiple locations in the code, sometimes in sub-sub-subroutines. First I tried to hand the sta...
BoonBengT_Altera's avatar
BoonBengT_Altera
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3 years ago

Hi @Christoph9,


Thank you for the patients, im trying to simulate the warning you have, unfortunately no luck in that.

If convenient perhaps you can share the .cpp files you have from your end for better understanding.


And as looking deeper into the warning message like you said compiler are using the barriers to synchronize memory accesses across threads.

My guess is that are more toward the loop pipelining part, perhaps you can try upon compilation to disabled the loops pipelining options. (More details on the link here --> https://www.intel.com/content/dam/develop/external/us/en/documents/oneapi-dpcpp-fpga-optimization-guide.pdf#page=171&zoom=100,0,572)

Hope that clarify.


Best Wishes

BB