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Shifali15
New Contributor
New ContributorL- and H-tile Avalon Streaming Intel FPGA IP for PCI Express as a Root Port
Hi, I want to use L- and H-tile Avalon Streaming Intel FPGA IP for PCI Express as a Root Port. But i not able to understand formation of TLP packets and how to form the TLP header, so please sugges...
Wincent_Altera
Regular Contributor
Regular ContributorHi,
Thanks for reaching,
- For PCIe Avalon ST L and H Tile Root Port procedure you may refer document at link below
- https://www.intel.com/content/www/us/en/docs/programmable/683111/21-1/root-port-enumeration.html
- TLP header information you may refer to same user guide as well
- https://www.intel.com/content/www/us/en/docs/programmable/683111/21-1/tlp-header-and-data-alignment-for-the.html
Hope this able to help, let me know if any further clarification is needed.
Regards,
Wincent_Intel
Shifali15New Contributor
New ContributorThank you for your reply,
- Is there any example designs available to understand the formation of these TLP headers?
- I want to understand what are those pcie_hdr_byte0 , pcie_hdr_byte1..........pcie_hdr_byte15 is there any documents to explain these headers?
