New Contributor
New ContributorI am in a similar situation. Trying to compile the example kernel from the loopback host pipe example on Arria 10 nodes (137-139)
I get the same error as discussed in an older forum post.
Occasional ContributorI'm curious what application you want to run on the Arria 10 GX board that the A10 PAC cannot support? We can investigate installing that board, but it could take a month or longer as we need another server blade - all are occupied with PAC boards.
Thanks
Larry
New ContributorWhy just not to add Software support for host pipes to Intel PAC card? This should be less than a month, it is just a software update!
Our application is confidential at the moment. However, the convenience of pumping data via host channels has advantage of having much less code than handling ping-pong buffers with events, etc. And we all for less code and conveniences, correct?
New Contributor@Lawrence_L_Intel Hi Larry,
I am trying to use the host pipe example from https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/opencl/host-pipe.html
On the host side, the application makes use clMapHostPipeIntelFPGA API via function pointers.
map_pipe_fn = (void * (*) (cl_mem, cl_map_flags, size_t, size_t *, cl_int *)) clGetExtensionFunctionAddress("clMapHostPipeIntelFPGA"); unmap_pipe_fn = (cl_int (*) (cl_mem, void *, size_t, size_t *)) clGetExtensionFunctionAddress("clUnmapHostPipeIntelFPGA");
The kernel arguments in the kernel are as follows:
#pragma OPENCL EXTENSION cl_intel_fpga_host_pipe : enable __kernel void loopback_hostpipe( __attribute__((intel_host_accessible, blocking)) __read_only pipe ulong4 host_in, __attribute__((intel_host_accessible, blocking)) __write_only pipe ulong4 device_out, ulong length, uint nostop ) { //kernel logic.... }
The requirements mentioned in the link I shared are
New ContributorThis is the summary of my attempts to compile the same example on Devcloud nodes.
On the Arria 10 PAC Compilation and Programming - RTL AFU, OpenCL node(S001-n139):
(Error while compiling the kernel)
aoc: Running OpenCL parser.... warning: unknown OpenCL extension 'cl_intel_fpga_host_pipe' - ignoring #pragma OPENCL EXTENSION cl_intel_fpga_host_pipe : enable ^ warning: expression result unused read_pipe(host_in, &data); ^~~~~~~~~~~~~~~~~~~~~~~~~ warning: expression result unused write_pipe(device_out, &data); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3 warnings generated. aoc: Optimizing and doing static analysis of code... Error: Channel has no point connection: ID= host_to_dev avm_channel_id_host_to_dev_read connection missing, or optimized away Error: Could not write system script to file. System generation aborted! Error: System integrator FAILED.
The host code compiles without any errors.
On the Stratix 10 PAC Compilation and Programming - RTL AFU, OpenCL node(S005-n008):
(Error while compiling the host)
host/src/main.cpp:133:12: error: ‘clCreatePipe’ was not declared in this scope &status);
While I am using this example to get familiar with the host pipes, In our lab, we intend to use host pipes in applications where streaming of data from CPU-> FPGA can take place. We could simply transfer the data before invoking the kernels, but we are interested in evaluating the performance of this streaming approach (overlapping CPU->FPGA data transfer with kernel execution)
