Hi,
Thanks you for your information and feedback. I will report this to the developer.
According to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/hls/ug-hls.pdf, Intel HLS compiler compiles the design to an x86-64 object or FPGA-targeted RTL code, and creates an executable testbench.
After compilation in HLS, you may saw the HDL file in component directory.
Also, you can use the command "eg: i++ --quartus-compile --simulator none -march=CycloneV counter.cpp -o test-fpga -v" and the results and files will be put in .prj/quartus directory.
For you information, the HLS compiler Lite v19.1 can be download as standalone software from https://fpgasoftware.intel.com/19.1/?edition=lite
Thanks