Generated code by Intel HLS does not work

Sorry for the missing file. I have attached it (with additional testbench files)

To run the simulation, I have done the following:

1. Create an empty folder (i.e., C:\testbench)
2. Launch "ModelSim - Intel FPGA Starter Edition"
3. Within ModelSim, create a new project (inside the folder of step 1)
4. Add all HLD (*.sv, *.v and *.vhdl) from from the generated Intel HLS project. Use the "Add Existing FIle" option and add the files located inside the following directories:
   1. hls\Target00\Target00.prj\components\%kernel%\*
   2. hls\Target00\Target00.prj\components\%kernel%\ip\*
   3. hls\Target00\Target00.prj\components\%kernel%\windows64\lib\dspba\Libraries\vhdl\base\*
5. Also add the testbench files (see attached zip)
   1. avalon_mm_adapter.vhd
   2. Target00_top.vhd
   3. top.vhd
6. In the project tab, select all Verilog files and:
   1. Right-click and select "Properties"
   2. Click on the "Verilog & SystemVerilog" tab and select "Use SystemVerilog" for the "Language Syntax" option.
7. Generate the compile order by selecting "Compile" and "Compile Order" in the tool bar. Then click "Auto Generate"
8. Launch the simulation with the following command vsim -gui -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim work.top
9. Add the required signals add wave -position end sim:/top/system_inst/*
10. Start the simulation with the run command for about 2000 ns