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fpgalearner's avatar
fpgalearner
Icon for New Contributor rankNew Contributor
7 years ago
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Fluctuation in the execution time results for OpenCL applications on Stratix V FPGA board.

Hi, I have a concern with the execution time results that I get from the Intel SDK Profiler. I am running rodinia applications using the Intel SDK HLS 16.0 on the Stratix V board. The profiler repor...
  • HRZ's avatar
    HRZ
    7 years ago

    The profiler is not made for timing measurement, it is made for detecting bottlenecks. Since the profiler dumps data onto the disk during execution, it could cause significant overhead and fluctuation in the run time. Use a host side timer (e.g. gettimeofday()) or the "clGetEventProfilingInfo()" function provided by the OpenCL standard to measure run time instead. 20-30 ms of fluctuation could be normal if run time is in the order of multiple seconds. Furthermore, for short benchmarks with random memory accesses, run time fluctuation could be high due to variable run-time scheduling of memory accesses.

    P.S. You might want to take a look at this repository which already has some of the Rodinia benchmarks ported for Intel FPGAs and already has host side timers in place:

    https://github.com/fpga-opencl-benchmarks/rodinia_fpga

HRZ's avatar
HRZ
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

The profiler is not made for timing measurement, it is made for detecting bottlenecks. Since the profiler dumps data onto the disk during execution, it could cause significant overhead and fluctuation in the run time. Use a host side timer (e.g. gettimeofday()) or the "clGetEventProfilingInfo()" function provided by the OpenCL standard to measure run time instead. 20-30 ms of fluctuation could be normal if run time is in the order of multiple seconds. Furthermore, for short benchmarks with random memory accesses, run time fluctuation could be high due to variable run-time scheduling of memory accesses.

P.S. You might want to take a look at this repository which already has some of the Rodinia benchmarks ported for Intel FPGAs and already has host side timers in place:

https://github.com/fpga-opencl-benchmarks/rodinia_fpga