Error running DLA Benchmark

Hi,

The HILO memory module should have the label on it. May I know if you are able to see the label?

Hi,

I try to convert the model provided by you and it looks like it is not be able to fully run in FPGA. The model will need to run on both CPU and FPGA.

I suspect that the hang issue might be due to the CPU side. The testing that was done is on Resnet model which can be fully run in FPGA.

Below is the summary of the analysis when converting the model.

List of reasons for unsupporting layers:

- Transpose_1482: General reshape is not supported when the input surface size (HxWxD) is greater than 10 or when CVEC != KVEC or when target_surface_size * CVEC (0) > 8192.

- Transpose_1482: General reshape is not supported when the target channel dimension is greater than the input channel dimension

Original graph per layer support information analysis:

Original Layer Name: Identity

Causative reasons for CPU placement:

- Transpose_1482: General reshape is not supported when the input surface size (HxWxD) is greater than 10 or when CVEC != KVEC or when target_surface_size * CVEC (0) > 8192.

- Transpose_1482: General reshape is not supported when the target channel dimension is greater than the input channel dimension

Original Layer Name: Transpose_1482

Causative reasons for CPU placement:

- Transpose_1482: General reshape is not supported when the input surface size (HxWxD) is greater than 10 or when CVEC != KVEC or when target_surface_size * CVEC (0) > 8192.

- Transpose_1482: General reshape is not supported when the target channel dimension is greater than the input channel dimension

Original Layer Name: Constant_5670

Causative reasons for CPU placement:

- Transpose_1482: General reshape is not supported when the input surface size (HxWxD) is greater than 10 or when CVEC != KVEC or when target_surface_size * CVEC (0) > 8192.

- Transpose_1482: General reshape is not supported when the target channel dimension is greater than the input channel dimension

Hi,

Can you try to run the model that we have verified to see if the issue persist as well?

Hi,

If you look the svg file, the 1st 2 node is run on CPU and not FPGA.

<!-- Reshape_552 -->

<g id="node1" class="node">

<title>Reshape_552</title>

<polygon fill="cornflowerblue" stroke="black" points="4751,-202 4645,-202 4645,-119 4751,-119 4751,-202"/>

<text text-anchor="middle" x="4698" y="-186.8" font-family="Times,serif" font-size="14.00">Transpose_1482</text>

<text text-anchor="middle" x="4698" y="-171.8" font-family="Times,serif" font-size="14.00">Reshape_552</text>

<text text-anchor="middle" x="4698" y="-156.8" font-family="Times,serif" font-size="14.00">Reshape</text>

<text text-anchor="middle" x="4698" y="-141.8" font-family="Times,serif" font-size="14.00">subgraph=82</text>

<text text-anchor="middle" x="4698" y="-126.8" font-family="Times,serif" font-size="14.00">device=CPU</text>

</g>

<!-- Result_556 -->

<g id="node2" class="node">

<title>Result_556</title>

<polygon fill="cornflowerblue" stroke="crimson" stroke-width="1.5" points="4742,-83 4654,-83 4654,0 4742,0 4742,-83"/>

<text text-anchor="middle" x="4698" y="-67.8" font-family="Times,serif" font-size="14.00">Identity</text>

<text text-anchor="middle" x="4698" y="-52.8" font-family="Times,serif" font-size="14.00">Result_556</text>

<text text-anchor="middle" x="4698" y="-37.8" font-family="Times,serif" font-size="14.00">Result</text>

<text text-anchor="middle" x="4698" y="-22.8" font-family="Times,serif" font-size="14.00">subgraph=82</text>

<text text-anchor="middle" x="4698" y="-7.8" font-family="Times,serif" font-size="14.00">device=CPU</text>

</g>

Hi,

May I know if you have any other queries or update on this?

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