New Contributor
Hi,
You may need a dual clock FIFO to transfer data between two different clock domains.
Regards -SK
Regular ContributorYou probably need to use the ModelPrim library to build it, there is a list of components that you can use to customize based on your design requirement (e.,g create a counter to control the valid signal to drop off those unnecessary samples).
Regards -SK
New ContributorThank you for the suggestion.
I decided to downsample my data signal by simply feeding it to a separate DSPBuilder-generated IP core running at a lower clock rate. Using the 0L latch block in DSPBA blockset to sample-and-hold my signals does not achieve the downsampling functionality that I am looking for, as this sample-and-hold algorithm adds high frequency content to my signal with jagged stair steps, as opposed to simply undersampling my signal.
Do you have any tips on how to implement a super-sampling mux and an undersampling demux?
Examples of these systems implemented with the Xilinx System Generator Blockset (similar to DSPBA blockset but for Xilinx FPGAs) is shown below.
The mux shown below has 32 input signals, which are outputted as a supersampled signal running at 32x the clock frequency of the input signals.
The demux shown below has one input signal which is time-division-demuxed to output to 32 signals, each at 32x lower clock frequency.
