DL models on FPGA with OpenVINO

Hi JohnT_Intel,

yes I just contacted Terasic about that question, thanks so much for the advice.

However, I don't know if you can help me with a more general question.

Do the levels supported by the FPGA plug-in depend on the particular FPGA or are they the same for all supported FPGAs?

(e.g. Intel Arria 10 GX FPGA Development Kit, Intel Programmable Acceleration Card with Intel Arria 10 GX FPGA, "Starter Kit for OpenVINO toolkit" with Cyclone V, "DE5a-Net-DDR4" with Arria 10, etc.).

I ask this because I found this link:

https://docs.openvino.ai/archive/2019_R1/_docs_IE_DG_supported_plugins_Supported_Devices.html

which shows in the section "Supported Layers" the levels supported by the FPGA plug-in: What does it refer to?

In addition, in the Intel distribution of OpenVINO toolkit 2019 R1 with FPGA support, I found bitstream files with DL model names, for example "2019R1_RC_FP16_MobileNet_Clamp.aocx" or "2019R1_RC_FP16_ResNet_SqueezeNet_VGG.aocx", in "/opt/intel/2019_r1/openvino/bitsreams/" path.

I was wondering what these files were and how you can use them.

Thanks in advance,

Best regards,
Vincenzo.