Cycle accurate simulation of OpenCL kernel

@HRZ Not true. You can simulate accurately entire OpenCL FPGA with DDRx chips models. How do you think Aletra/Intel Enginners got it working? But noone should take up such large effort unless they have no other choice.

@UMinh The DDR4 controller latency is pretty much fixed and you can find it out from simulations (see below) or SignalTap. What you are really interested in are latency and throughput from OpenCL kernel(s) global bus masters to Avalon global bus interface to DDR4 controller. This interface is in top.v at <platform>/hardware/<board> or a10_ref/hardware/a10gx for example. You can replace board interface DDRx by Avalon Bus Functional Model. Then you have to start OpenCL kernel via CRA registers with register values that you can obtain (e.g. from SignalTap or API/PCIe driver/MMD/HAL debug level logs) for various kernels that you have. The CRA registers are in <kernel>/kernel_hld/<kernel>/<kernel>_function_cra_slave.sv. Contact me on LinkedIn https://www.linkedin.com/in/drfpga/ if you need help to get this going quickly.