Create call signals in Platform Designer to run IP block

Thank you for this helpful information.

I'm not sure if "call and return signal" is transfer data or read data of the IP block. I can't find any documentation on these signals and how they are generated by a function call by value in HLS. Are these signals generated just for the testbench or are they needed for communication between IP blocks. The following picture is the generated counter example in Platform Designer.

Is there an existing example how to generate an IP block in HLS, implement it in Platform Designer and run it on a FPGA.

Thanks!