Most RecentWhy does OpenCL™ API clGetKernelArgInfo() run fail?Error: Received error code -42 on line 122 in host/src/OpenCL.cError: kernel_mem_mm_bridge_0: deviceFamily "Arria 10" is out of range: "Cyclone 10 GX", "None", "Unknown"External I/O Channels Unavailable in Custom Platforms Ported from the Altera Stratix V Network Reference PlatformWhy does my OpenCL 17.0 BSP import compile show false timing failures?warning: xx.cl:x:x: loop not unrolled: the optimizer was unable to perform the requested transformation; the transformation might be disabled or specified as part of an unsupported transformation orderingError (13224): Verilog HDL or VHDL error at <kernel_filename>.v: ansi port p_avm_printf_addrhello_world_enable cannot be redeclaredError: "cannot find board_env.xml in ..."Can Intel® Stratix® 10 GX FPGA Development Kit support PCIe gen3x16 for OpenCL™?Error (297008): Can't create database directory for project in project directory
