Most RecentWhy does Nios® V processor simulation fail when using the generated VHDL testbench from Platform Designer?Why does my PCIe* Independent GPIO PERST# test design fail to compile when I target the GXF_2ND_PERSTn signal on Pin CN11 of the Agilex™ 7 FPGA F-Series Development Kit (2x F-Tile) (AGF023)?Why is U-Boot not able to configure the Agilex™ 5 and Agilex™ 3 SDMMC controller in 8-bit bus width when booting from eMMC in releases 25.1.1 and before, regardless of bus-width = <8>; parameter is defined in the device tree?How accurate are the CDR Function Pins in the Agilex™ 5 FPGA, Agilex™ 7 FPGA M-Series, and Agilex™ 3 FPGA Pinout Files?Why are there functional failures after partial reconfiguration in Agilex™ 7/5/3 FPGA designs?Does the Agilex™ 5/3 FPGA HPS EMIF support the External Memory Interface Debug Toolkit?Is there a known issue with the behavior of the nCATTRIP signal in Agilex™ 5 FPGA and Agilex™ 3 FPGA devices?Why is the CRAM integrity check feature not working on Agilex™ 5 FPGA and Agilex™ 3 FPGA devices?Why can’t I place the bytes of two LVDS SERDES IP instances (in TX or Non-DPA RX modes) to the same IO sub-bank on Agilex™ 5 in Quartus® Prime Pro Edition Design Software versions prior to 25.3?Does Agilex™ 3 support SmartVID optional functions for some pin names in the Quartus® Prime Pro Edition Software?
