Most RecentWhy do some compilations of my design with the Intel® L-/H-Tile Avalon® streaming IP for PCI Express* result in an unresponsive PCI Express* link?How do I create or edit an ALTLVDS_RX Intel® FPGA IP for Intel® Cyclone® device series using the Quartus® II software version 10.0?Why pause frame without FCS (CRC) field is transmitted by the 10G Ethernet MAC?Why don't reset_rx_clk and reset_tx_clk signals of PCS-only variant and PCS plus PMA variant of the Triple Speed Ethernet Intel FPGA IP synchronize to the rx_clk and tx_clk signals?Why will PMA of Triple Speed Ethernet Intel® FPGA IP undergo a reset sequence automatically whenever rx_freqlocked is lost?Error (292019): Core Nios® II Processor (6AF7_00A2) is not enabled for current device familyWhy Triple Speed Ethernet Intel® FPGA IP instances transmit and receive PLL for LVDS I/O fail to share the same PLL?Why does the Triple Speed Ethernet Intel® FPGA IP receive packet error in 10/100Mbps when the MAC's local loopback is enabled?Why is there a hold slack difference when performing timing analysis using the -force_dat option in the Timing Analyzer?Why does Nios® II Software Build Tools for Eclipse hang when you try to run a project as Nios® II hardware ?
