Why Triple Speed Ethernet Intel® FPGA IP instances transmit and receive PLL for LVDS I/O fail to share the same PLL?

Description

 Triple Speed Ethernet Intel® FPGA IP instances transmit and receive phase-locked loop (PLL) for LVDS I/O fail to share the same PLL.

 

Resolution

The following patch provides a solution to ensure transmit and receive PLL for LVDS I/O can share the same PLL.

Download the appropriate Quartus® II software version 10.1SP1 patch 1.77 from the following links:

• Quartus II software version 10.1SP1 patch 1.77 for Windows
• Quartus II software version 10.1SP1 patch 1.77 for Linux
• Quartus II software version 10.1SP1 ReadMe for patch 1.77

Caution:

You must either have previously installed the Quartus II 10.1 SP1 software or must install the Quartus II 10.1 SP1 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.

After you install the patch, regenerate your Triple Speed Ethernet Intel® FPGA IP before you compile your design.