Most RecentError (10170): Verilog HDL syntax error at <location> near text "generate"; expecting "end", or an identifier ("generate" is a reserved keyword ), or a sequential statementWhy the designs fail compilation when Enable TX PLL is selected for SDI Dual Link?Internal Error: Sub-system: CUT, File: /quartus/db/cut/cut_stratixv_lc_pll_group.cpp, Line: 132 altera_xcvr_low_latency_phyWarning (332174): Ignored filter at outlvds_altera_lvds_core20_161_uedfafy.sdc(120)When in the configuration process will the CRC_ERROR pin be driven low if enabled?Error(15744): ( topology != EHIP_4CH_PTP_FEC ) in Intel® Quartus® Prime Software version 19.1 and earlierIs reconfiguration of the VCO post-scale divider supported in the Quartus® II software?If I am using the top ATX PLL in the bank and the ATX PLL supports the data rate for Stratix® V, can I ignore Critical Warning for ATX PLL Range?Can I power the HPS rails with a fixed voltage supply on SmartVID enabled Stratix® 10 FPGAs?The Symbol Editor context menu refers to the obsolete MegaWizard Plug-In Manager in the 14.0 Quartus II software release
