Most RecentWhy does the compilation time increases when global Advanced I/O Timing settings are used for the Stratix® 10 devices?Why are there timing violations on the *pld_fpll_shared_direct_async_out_hioint[2] clock domains within the Agilex™ 7 device F-Tile PMA/FEC Direct PHY Multirate FPGA IP?Are the default XAUI PHY IP transceiver PMA settings in Quartus II Software Version 10.1-SP1 and earlier capable of implementing a XAUI compliant link in Stratix IV GX and GT devices?Arria V Hard IP for PCI Express IP Core VOD Too LowWhy do I see "Error(18108): Can't place multiple pins assigned to pin location" in my design with Partial Reconfiguration?Transceivers are not preserved when the device remains powered and unprogrammed for an extended period of time.Critical Warning (127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File <file path> .hex -- setting all initial values to 0java.lang.UnsatisfiedLinkError: C:\altera\14.1\quartus\bin64\sld_utiljni.dll:Internal Error: Sub-system: U2B2_CDB, File: /quartus/db/u2b2/u2b2_nf_lab_ibr_module_lcb.cpp, Line: 498How do I set edge lines and active picture line for the Clocked Video Output (CVO, CVO-II)? Are there any guidelines for valid parameter settings for the CVO?
