Most RecentWhy does the serdes_pll_locked signal of upper PCI* Express Hard IP of Intel® Cyclone® V devices does not lock?Are there any known problems when trying to simulate the Quartus II software versions 12.1, or 12.1sp1 10GBASE-KR PHY IP in Cadence ncsim?Why does my PCIe link get stucked in the Detect state for Arria® II and Stratix® IV devices?java.lang.RuntimeException: Can't initialize DevFamilyManagerFromDB: connectivity to DB problemError (332000): can't read "pll_ref_clock": no such variableWhy does my OS freeze when using the Intel® Stratix® 10 PCIe Hard IP core?Why does my JIC programming operation fails at the 'Verify' step with the Quartus® Prime Pro Edition Software Programmer version 18.1Where can I download the schematics files for the FMC loopback daughter board designed for the Intel® Stratix® 10 SX SoC Development Kit?Why can't I configure my Intel® Stratix® 10 device using a . JAM file?Error: (vsim-3033) /io_buf.v(87): Instantiation of 'altiobuf_bidir' failed. The design unit was not found.
