Most RecentWhy are there functional failures after partial reconfiguration in Agilex™ 7/5/3 FPGA designs?Does the Agilex™ 5/3 FPGA HPS EMIF support the External Memory Interface Debug Toolkit?Is there a known issue with the behavior of the nCATTRIP signal in Agilex™ 5 FPGA and Agilex™ 3 FPGA devices?How to run Agilex™ Multiple EMIF Designer Tool in Agilex™ 7 FPGA and SoC FPGA M-Series, Agilex™ 5 FPGA and SoC FPGA, and Agilex™ 3 FPGA and SoC FPGA?Why is data packet loss due to CRC error observed in Agilex™ 5 and Agilex™ 3 TSN XCVR SGMII 1G mode?Why is the CRAM integrity check feature not working on Agilex™ 5 FPGA and Agilex™ 3 FPGA devices?Why can’t I place the bytes of two LVDS SERDES IP instances (in TX or Non-DPA RX modes) to the same IO sub-bank on Agilex™ 5 in Quartus® Prime Pro Edition Design Software versions prior to 25.3?Why do I see a large timing violation when using the IOPLL IP’s Non-Dedicated Feedback Path option?Does Agilex™ 3 support SmartVID optional functions for some pin names in the Quartus® Prime Pro Edition Software?Why do Agilex™ 5 FPGAs and Agilex™ 3 FPGAs SEU report incorrect bits position within the frame and/or combination of row and frame index in the Quartus® Prime Pro Edition 25.1?
