Most RecentWhy am I unable to set the 'Size of address pages' to a value between 17 and 21 bits for the Intel® Arria® 10 FPGA and Intel® Cyclone® 10 GX FPGA Hard IP for PCI Express in Avalon® memory-mapped mode?Warning (12030): Port "reconfig_from_xcvr" on the entity instantiation of "alt_pma_0" is connected to a signal of width 368. The formal width of the signal in the module is 230. The extra bits will be left dangling without any fan-out logic.Performance Risk Running Triple Speed Ethernet LVDS in Arria 10 DevicesAre there any issues with the UniPHY IP Global Signal assignments seen in the Quartus II software Assignments editor after running the <variation_name>_pin_assignments.tcl script?Why does the Intel® Arria® 10 and the Intel® Cyclone® 10 Avalon®-ST or Avalon® -MM Interface for PCI Express* IP example design report ignored SDC constraint warnings?Why is the “o_rx_pause” width as double as the expected value for 40GE designs when using the F-Tile Ethernet FPGA Hard IP and F-Tile Ethernet Multirate FPGA IP?During simulation of the 40- and 100-Gbps Ethernet MAC and PHY MegaCore Function, l8_rx_fcs_error goes to 'X' when l8_rx_fcs_valid is '1'Why do the FIR II Megacore’s parameters revert to default values after upgrading to a newer version of the Quartus software?Why after collision occurs for Triple Speed Ethernet IP MegaCore in half-duplex mode, MAC function continuously sends data out through the MII interface even when no data are sent to the MAC function?Can I run boundary scan on a JTAG chain that contains a Stratix II, Stratix, Cyclone II or Cyclone devices and is longer then 8 devices?
