Most RecentHi, whenever i try to run my circuit design in Quartus ii lite, I'm getting this error,Error (12004): Port "OUT1" does not exist in primitive "OR5" of instance "ssss". Is there any suggestions or solution for this. thanksHow can I include "Dont Care" in a transition state when designing a state machine.Pin is not stable when the device is powered up, how to deal with it please?Are there tools available to simulate Terasic DE2-115 development kits for education purposes?Quartus Prime Pro 19 complains about no license, but it is licensed. So, how can I confirm which versions are supported by my license ?hello , we are working on edge detection ( coin detecting ) with D5M camera on board de1 soc, we could not integrate camera to use by quartuse, is there anything to help us can run our camera?Arria10 PCIE exampleHi, Where should I ask for a VIP License?Why is the FPGA Monitor Program Editor (from the UPDS) disabled/not working?EOL (End Of Life) expectation for 10M08SCU169I7G
