Most RecentHi, Every I/O Bank in arria10 FPGA has only one I/O PLL in it. Can we use the same I/O PLL for all LVDS Serdes I/O channels in the same bank without using external I/O PLL IP? OR only one LVDS channel can use the I/O PLL provided in the particular bank?Hi, I just downloaded the Web Edition of Quartus II 13.0sp for ubuntu18.04 but when I tried running 'sudo ./setup.sh' I got a warning: libpng warning: Application jmp_buf size changed Segmentation faultQuartus 18.1 Lite on Windows 10: DDR3L SDRAM Uniphy, IP core generation FAILS.why qsys use type "logic" for inout? inouts are nets by definition, not variable.java exception when opening top level QSYS designabout the error: Error (169079): Pad 51 of non-differential I/O pin 'I2[5]' in pin location N8 is too close to pad 49 of differential I/O pin 'inclk0' in pin location M7 -- pads must be separated by a minimum of 5 pads.I2CスレーブIPを使う時の端子のIO規格や内部クロックの推奨は？Unable to use licenses concurrentlyI am confused about the Equation 5 in the AN433Does anyone have a working project with "I2C Slave To Avalon-MM Master Bridge intel FPGA IP"?
