Most RecentSignalTap issueIn Signal Tap, I have set trigger conditions on more than one signal(tapping on AXI signals). I have set to Basic AND condition on 2 signals while rest of them are don't care . Can I expect a capture correctly?Shortening NIOSII Simulation run time with FPGA SOC system as recommended in AN351Altera training videos no longer work in FireFoxIs the systemverilog "case inside" statement for definitions of a range of conditions within a case block available for synthesis and, if not, when will this be implemented?Error(16169): Instance "" has an ambiguous entity bindingQuartus II Web Edition Software v7.2 licensingLicense server service not startingWarning (12620): Input port OE of I/O output buffer "hps_i2c0_SDA~output" is not connected, but the atom is driving a bi-directional pinI am getting "Internal Error: Sub-system: CDB, File: /quartus/db/cdb/cdb_lutmask.cpp, Line: 566" from Quartus II 12.1
