Most RecentPLL Cascade bandwidth configuration issues (fPLL)Is it possible to connect the output of a Cyclone V dynamic delay chain to an ALTLVDS_RX SERDES receiver?What pins should be used for PCIe hard IP (on Arria 10)Is anyone running Arria 10 FPGA EMIF IP functional simulation with Questasim simulatorcan we implement PCIe root port on cyclone v gt development board ?? and the board is having pice 4x edge connector (male) not female one, so does that is required for root port feasibility??I would like to know the required voltage level (VCCR_GXB and VCCT_GXB) for the tranceiver and receiver bank of the 10AS022C3U19I2SG to support PCIe Gen.3.hello, I'm trying to program a cpld , but i didn't find the .sof file, i just have the .pof file any solutions? best regradshello, my testbench work on simulation , but not on board what should I do please thank youQuartus lite and Standard included IPsI am working on MAX 10 FPGA interfacing with SI5338B using I2C. I have used NIOS 2 and integration done using Qsys. However, I am not getting ACK response from slave device. Could you please provide me support on this? Can I get similar project for study?
