Most RecentDear INTEL, Thanks for PCIE hardIP+ with HBM2 reference designs. The reference design are not available to download even after sign-in.encrypt my IPA10 DDR4 Hard Controller AVMM Operation / Timing Diagramfft_ii_0 is not boundmultiple MSI using PCIe with Avalon-MMprogramming problem with new Generic Serial Flash Interface Intel FPGA IP Core.Can the PCI Express Hard IP support, not RP nor EP, but instead "Switch" Mode?Is a multiport TSE MAC with 2PHY's and 1 MDIO interface possible?Hi everyone, Is there a mapping between the JTAG interface and the TSE IP for setting registers? how could I use the register settings from the tcl script in my vhdl design?What alternative we have to LPM_ADD_SUB for Arria10 device. I want to use carry chain logic to use it as delay element. Looks like LPM_ADD_SUB is not supported for Arria 10 device. Please advise.
