Most RecentNeeds help on clarification on Scemi clock controladding 2 high speed reed solomon decoders increased the 'Logic Utilization' in 20% (only 7% was expected based on other project where i also added the same 2 high speed reed solomon decoders).PCI Express Hard IP Avalon-MM legacy interrupt handlingRequesting help in the proper installation and use of a user-defined VHDL package to be shared by multiple user IP instances in Platform DesignerDoes the request for the Multi-axis Motor Control reference design work for anybody? Me and my customer requested it and got no answer.The DDR2 Controller with UniPHY has a port called "afi_reset". What causes this signal to assert? We are experiencing this signal asserting on a small subset of custom fpga boards. We are trying to debug the exact cause.rst_n port on the pll is not properly connectedDoes the hardware H-tile 100G Ethernet needs additional licence?We are trying to build DMA design with PCIe P-Tile Hard IP. Need help with AN456 reference design for PTile HardIPALTPLL Error: Clock Input port of PLL must be driven by non-inverted input pin or another PLL.
