Most RecentHey, I would like to use HyperBus memory. My board will contain cyclone V too. My question is, how the clock pin in the HyperBus should be connected? To a standard IO of the FPGA or to a dedicated CLK pin. Best regards, PelegWe are using Altera Cyclone IV EP4CE10. Does it provide SPI based FPGA programming as Xilinx provides?How do I develop with a legacy CPLD Max3000a?PCIe: Which devices supports more then one Virtual Channel (VC)?i am using MAX 10 with external CFI NOR flash for FPGA ST10 image. for FPGA configuration using "PFL II IP core " . the problem is how we can update the NOR flash image from remote (not from JTAG connector) .Replacement for LXT905Intel Arria 10 GX FPGA (DK-ACB-10AX1152AES) compatible with Dell R540 ?Interface LVDS signals to the FPGA cyclone V GX.do you need different drivers for reference clocks for A10GX?Cyclone 10 GX: unused GX Transceiver
