Most RecentError running Very Basic Operation on Stratix 10 SX SoC Dev KitADV2002 Customer Advisory - INQUIRYGeneral I/O clarificationsQuartus 13.1 cpu usage reports incorrect with 72 cores machines.In Arria V (5AGXFB7K4F40I5) I have generated DDR3 memory controller (using Quartus IP catalog). Following power (long time) up signal mem_reset_n is stuck at low though cal_success is at '1' and other controller ouptus seem to OK What coud be reason?Can you tell me what the AB stands for on the EP2S30F484I4AB?Hi, We are using max10 fpga and in the fpga code to convert from 25MHz to 10kHz , the maximum count value of the counter is given a value of 12499. Could anyone please describe how to calculate this value? ThanksDo you happen to know what the “X” calls out at the end of Altera part number EPF10K100EBC356-1X?How to connect the 125 MHz clocks for HPS EMAC when routed to FPGA logic?Is the DDR's VTT0.6v required to be the same as that supplied by FPGA's DDR4 controller 1.2V?
