Most RecentSata 3 interface for Stratix IV GX .How to see Transceiver phy output (received parallel data) on putty terminal?I downloaded an741 example for fpga 10M50. When I opened it in Quartus prime software, I was able to compile factory_image and app_image_1 but I am not getting any option to compile app_image_2. What to do?Low Latency 100G MAC not producing light through Mellanox MMA1B00-C100D optical module in Stratix 10 Transceiver Signal Integrity KitI am using an Arrow SoCkit Cyclone V .programmer starts to run but fails after 60%Possible to configure fpga from hps by having fpga image in QSPI on Cyclone V SoC Development kit?I implement the "Altera User Flash Memory for I2C Interface Protocol" ip core in MAX V device, and I want to map the content of UFM's memory content to some I/O. Since I want to map the data of write operation to some I/0. But I don't know how to map.Is it possible to use Arria 10's transceiver with 64b/66b for custom data protocol?PCIE hard ip issue, when i try to integrate two PCIE hard IP's ,than synthesis is being failed.( family Cyclone V , gx )This is regarding below mentioned part numbers from Intel Altera FPGA cyclone family. EP4CE15F23I8LN EP4CE15F23I8N Want to know the difference between the two part numbers.
