ZKhan1
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Re: Active Serial Multi Device Configuration issue
Hi Aqid , This is proto A PCB , yes you right it will be corrected in proto B PCB. But i am thinking of ways to make it work , if possible as on the PCB i do have a separate flash connected to 2nd FPGA and i can program it without any problems . But my question is there is PCB_RESET_n comming from 1st FPGA to the 2nd FPGA , and some processing happens after RESET in the 2nd FPGA , because of this hardware problem this RESET will not be asserted by the 1st FPGA . Does this issue cause the configuration of the 1st FPGA to be NOT implemented / programmed at all , or it will always be in reset state . Because with the 2nd FPGA configuring with a separate Flash , their boot up time will be different . Because in testing i do see some communication possible between the two FPGA's , but some times its failing ? Regards , Ahmed1.1KViews0likes0CommentsActive Serial Multi Device Configuration issue
Hi , I have a board with x02 Cyclone 10 Lp , part number : 10CL040YF484C8G , they are connected in Active Serial Multi Device config with first FPGA the master configurer . But the schematic designer made a mistake and now i have nCE, CONF_DONE and nSTATUS signals not connected to the 2nd FPGA . Although CONF_DONE and nSTATUS are pulled high . Will this issue cause the first FPGA not configured properly ? or will this issue make it remain in reset state ? Regards , Thanks1.2KViews0likes4CommentsRe: Modelsim-Altera do file paths
Please read my initial post , in the working project all the altera ips .vhd and .qip files are in root directory of the project . But what i want is a separate folder for each ip and the modelsim be able to read from those folders each of the .vhd and .qip files .2.4KViews0likes0CommentsRe: Modelsim-Altera do file paths
All the relevant Nativelink settings are in place , this is after Modelsim is invoked and the testbench has been correctly setup. I have another version of this same project with successful simulation , but all the altera ip vhd and qip files are in root directory of the project . So back to my previous question , what cantt modelsim pick up the files from their folders ?2.5KViews0likes0CommentsRe: Modelsim-Altera do file paths
And this is how my user libraries are define in vhdl top file : LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; LIBRARY altera_ip; USE altera_ip.ALL; LIBRARY cyclone10lp; USE cyclone10lp.ALL; --LIBRARY cyclone10lp_components; USE cyclone10lp_components.ALL; LIBRARY lib_top_pas_rs_hssl_mk2_fw; USE lib_top_pas_rs_hssl_mk2_fw.ALL; LIBRARY lib_reset_crtl; USE lib_reset_crtl.ALL; LIBRARY lib_app_hbi; USE lib_app_hbi.ALL;2.5KViews0likes0CommentsRe: Modelsim-Altera do file paths
These are the Modelsim errors : vcom -93 -work work {C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pas_rs_hssl_mk2_fw/hssl_mk2_hbi_interface.vhd} # Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 13:27:30 on May 31,2022 # vcom -reportprogress 300 -93 -work work C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pas_rs_hssl_mk2_fw/hssl_mk2_hbi_interface.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # ** Error: C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pas_rs_hssl_mk2_fw/hssl_mk2_hbi_interface.vhd(45): (vcom-1598) Library "lib_top_pas_rs_hssl_mk2_fw" not found. # ** Error: C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pas_rs_hssl_mk2_fw/hssl_mk2_hbi_interface.vhd(46): (vcom-1136) Unknown identifier "lib_top_pas_rs_hssl_mk2_fw". # ** Error: C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pas_rs_hssl_mk2_fw/hssl_mk2_hbi_interface.vhd(48): VHDL Compiler exiting # End time: 13:27:30 on May 31,2022, Elapsed time: 0:00:00 # Errors: 3, Warnings: 0 # ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vcom failed. # Error in macro ./top_pas_rs_hssl_mk2_fw_run_msim_rtl_vhdl.do line 14 # C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vcom failed. # while executing # "vcom -93 -work work {C:/intelFPGA_lite/18.1/quartus/qdesigns/top_pas_rs_hssl_mk2/hdl/lib_top_pa2.5KViews0likes0CommentsModelsim-Altera do file paths
HI , I have a design in which i have placed all ip that i have used in separate folders like for pll i have put the generated files in altera_pll , for dpram in altera_dpram . I can compile the design in Quartus Prime ver 18.1 , but when try to run simulation the modelsim complaines about "library found " etc . I tried to edit the .do file , but it is over written . Is there a way to run the simulation with this setup ? Regards , Ahmed2.6KViews0likes10CommentsRe: VHDL Package not detected by Modelsim
No it is not working: vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive_ver -L cycloneive -L rtl_work -L work -L Fir_left_ch -voptargs="+acc" tb_audio_ctrl_Top.vhd # vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive_ver -L cycloneive -L rtl_work -L work -L Fir_left_ch -voptargs=""+acc"" tb_audio_ctrl_Top.vhd # Start time: 09:16:35 on Apr 15,2022 # ** Error: (vsim-19) Failed to access library 'tb_audio_ctrl_Top' at "tb_audio_ctrl_Top". # # No such file or directory. (errno = ENOENT) # Error loading design # Error: Error loading design # Pausing macro execution # MACRO ./Audio_FIR_filter_run_msim_rtl_vhdl.do PAUSED at line 76 vmap -c # Model Technology ModelSim ALTERA vmap 10.4d Lib Mapping Utility 2015.12 Dec 30 2015 # vmap -c # ** Warning: vmap will not overwrite local modelsim.ini.1.4KViews0likes0Comments