chander
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Re: Agilex 7 can HPS use HBM instead of DDR to connect to MPFE
Hi, The query was regarding the HPS being able to access the HBM over the MPFE interface rather than the AXI interface. The HPS can only access a 4GB address space over the HPS-to-FPGA AXI interface, however via the MPFE it can access 16GB address space or more. The query was if HPS can access the HBM via MPFE. regards Chander1.3KViews0likes0CommentsRe: Agilex 7 can HPS use HBM instead of DDR to connect to MPFE
Thanks Aik Eu, Should we then conclude that its not technically feasible to have the HPS access HBM via the MPFE? Or should we conclude that while its possible , there are no examples or documentation for it ? regards Chander1.5KViews0likes0CommentsRe: How to access entire 4GB DDR from Agilex 7 HPS
Hi Aik Eu, Do we also need to make changes to the firewall_ddr_fpga2sdram_inst_0_scr registers? Could you tell us the changes needed in u-boot-socfpga/arch/arm/mach-socfpga/spl_agilex7.c if any ? We are using AGMF039 device. regards Chander1.6KViews0likes0CommentsRe: Agilex 7 can HPS use HBM instead of DDR to connect to MPFE
Thanks for the link, it contains some wonderful design examples, but unfortunately not what we need. Btw is it architecturally possible to have the HPS boot of the HBM instead of DDR via the MPFE? If so can someone guide us how we can possibly achieve this.1.8KViews0likes0CommentsRe: How to access entire 4GB DDR from Agilex 7 HPS
Hi, We made following changes to u-boot-socfpga/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi memory { /* 4GB */ reg = <0 0x00000000 0 0x80000000>, <0x10 0x80000000 0 0x80000000>; }; Apart from this we made the following change in u-boot-socfpga/arch/arm/mach-socfpga/spl_agilex7.c writel(0x80000000, 0xF8020110); // region0addr_base writel(0x10, 0xF8020114); // region0addr_baseext writel(0xFFFFFFFF, 0xF8020118); // region0addr_limit (lower 32bits) writel(0x10, 0xF802011C); //region0addr_limitext (upper 32bits) writel(0x1, 0xF8020104); //enable_set for regions writel(0x80000000, 0xF8020210); // region0addr_base writel(0x10, 0xF8020214); // region0addr_baseext writel(0xFFFFFFFF, 0xF8020218); // region0addr_limit (lower 32bits) writel(0x10, 0xF802021C); //region0addr_limitext (upper 32bits) writel(0x1, 0xF8020204); //enable_set for regions writel(0x1, 0xF8020204); //enable_set for regions But in the uboot , the md 0x1080000000 1 , hangs1.7KViews0likes0CommentsAgilex 7 can HPS use HBM instead of DDR to connect to MPFE
AGMF039 has 32GB of HBM. 16GB of HBM is on the same NoC as HPS. Is it possible for HPS to use this 16GB (or perhaps even 32GB) of HBM to be connected to its MPFE interface instead of DDR. Is there any example design for the same?Solved1.9KViews0likes12CommentsHow to access entire 4GB DDR from Agilex 7 HPS
We have a configuration where the Agilex 7 HPS EMIF interface is connected to 4GB DDR on the board. However the Linux/uboot is able to access only 2GB i.e address 0x0 - 0x7FFF_FFFF, while from F2H Acelite interface we can access the entire 4GB 0x0 - 0xFFFF_FFFF. The Agilex™ 7 Hard Processor System Technical Reference Manual , does https://www.intel.com/content/www/us/en/support/programmable/articles/000090809.html But even after enabling that we aren't able to access the address 0x10_8000_0000 - 0x10_FFFF_FFFF neither from the uboot using "md" command nor from the acelite. The app note does refer to Stratix10 instead of Agilex7 , so not sure if its even relevant. Any pointers on how to access the entire 4GB DDR from HPS in Agilex7.1.8KViews0likes9Comments