AlanCLTan
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Re: 25.3 PRO Release
Hi Arun, USB3.1 in Host mode is enabled by default in Agilex 5, including 25.1. The workaround in USB 3.1 Gen-1 Controller Tutorial Example Design User Guide is mainly to enable the Device mode (a change from the Host mode), using 25.1.1. May I know how you see the device being detected as USB2.0?48Views1like5CommentsRe: Operating system kernel-level FPGA bridge communication
Hi Arun, devmem2 is the most common and easiest way to access a FPGA bridge from Linux kernel, to do it another way, you could try adding a node similar to https://www.kernel.org/doc/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt into https://github.com/altera-fpga/linux-socfpga/blob/QPDS25.1_REL_GSRD_PR/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts, but with another values for register range, reset, and clock. You will also need a custom driver to access the node you created.59Views0likes5CommentsRe: Operating system kernel-level FPGA bridge communication
Can you try running "bridge enable" in the U-boot Shell? You may refer to https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-7/f-series/soc/boot-examples/ug-linux-boot-agx7-soc/#enabling-bridges-from-u-boot (the same method works for Agilex5)88Views1like1CommentRe: Gate Level Simulation
Hi, Could you try an experiments to see if it solves the error: 1. Remove the generic entity declaration, including GPIO_WIDTH, from the component declaration? component UART_Top port ( -- your ports here ); end component; ---------------------------------- Remove the generic map from the instantiation? UUT: UART_Top port map( -- your port mappings ); ---------------------------------- Best regards, Alan Tan583Views0likes0CommentsRe: Gate Level Simulation
Hi, The comparison of your component declaration in the testbench and the component declaration of UART_Top, one port is found missing: UART_TXD : OUT STD_LOGIC; Even though the error message complains about GPIO_WIDTH, the actual issue is likely due to incomplete port matching between the component and the entity. Please check again. Best regards, Alan Tan1.2KViews0likes2CommentsRe: '*.vho not found' in Modelsim ALTERA
Hi, Please ensure IP Generation is complete. Make sure the IP core has been fully generated using the IP Catalog. This process should create the necessary simulation files. 1. Use the EDA Netlist Writer Quartus uses the EDA Netlist Writer to generate simulation files like .vho (VHDL Output). For configuration steps: Go to Assignments > Settings > EDA Tool Settings > Simulation. Choose ModelSim-Altera as the tool. Set the Format to VHDL. Under Output, ensure Generate simulation netlist is checked. 2. After setting up the simulation tool: Go to Tools > Run EDA Simulation Tool > RTL Simulation or manually run the EDA Netlist Writer via: quartus_eda --simulation <project_name> This typically generates the .vho file for the top-level design. However, if you need the .vho for the IP module itself, you may need to: Open the IP folder (usually under ip/<ip_name>/simulation/). Look for .vho or regenerate using the IP generation tool with simulation files enabled. Best regards, Alan Tan1.3KViews0likes0Comments