AlanCLTan
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Re: Cyclone5 SoC: U-Boot not detecting USB-HUB
Hi teiram, Let's try these: 1. Do you have a PHY node for USB3300 in the your previous working u-boot? Something like the example below. Add it into the dtsi: { /* Define the PHY node outside the soc bus */ usb_phy0: usb-phy { compatible = "usb-nop-xceiv"; #phy-cells = <0>; reset-gpios = <&portb 0 GPIO_ACTIVE_LOW>; status = "okay"; }; }; &usb1 { status = "okay"; dr_mode = "host"; // Usually 'host' for Cyclone V boards usb-phy = <&usb_phy0>; // Link to the PHY node }; 2. Make sure the Linux kconfig options (set in defconfig) are set: CONFIG_USB_DWC2=y CONFIG_USB_OHCI_HCD=y --- sometimes needed for full/low speed support CONFIG_PHY=y CONFIG_NOP_USB_XCEIV=y --- Essential if using the usb-nop-xceiv compatible string. CONFIG_USB_ULPI=y --- Required for the ULPI interface protocol. 3. The USB3300 or an downstream hub requires specific GPIO states to be enabled before the USB stack starts. You can do this in U-Boot with: gpio set 9 usb start5Views0likes0CommentsRe: Cyclone V: how to enable USB1 with a ULPI USB PHY (USB3320)?
Hi dpeng, Let me understand further on your setup: CPEN routed to a VBUS power switch enable (active‑high) RESET# of the USB3320 driven by HPS_GPIO0 (active‑low) Is that correct? Could you confirm the checklist below: Confirm the 5 V input to the VBUS power switch is present. Verify the switch enable pin is active-high and connected to CPEN directly. Verify the reference clock to USP3320 (26MHz) is present and stable. Scope the ULPI CLK pin from the PHY (usually 60 MHz output to the MAC). Also check that ULPI I/O voltage rails (1.8 V or 3.3 V) are correct. For OTG micro‑AB, ID grounded: A‑device (host); ID floating: B‑device (peripheral). If the ID pin is floating, the PHY may not try to source VBUS. Best regards, Alan29Views0likes0CommentsRe: Cyclone V: how to boot Linux from QSPI?
Hi dpeng The latest 25.1std release for Cyclone V is now available. Please visit https://altera-fpga.github.io/rel-25.1/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/#2-cyclone-v-soc-boot-from-qspi for the way to boot from QSPI. Thanks, Alan20Views0likes0CommentsRe: 25.3 PRO Release
Hi Arun, USB3.1 in Host mode is enabled by default in Agilex 5, including 25.1. The workaround in USB 3.1 Gen-1 Controller Tutorial Example Design User Guide is mainly to enable the Device mode (a change from the Host mode), using 25.1.1. May I know how you see the device being detected as USB2.0?92Views1like6CommentsRe: Operating system kernel-level FPGA bridge communication
Hi Arun, devmem2 is the most common and easiest way to access a FPGA bridge from Linux kernel, to do it another way, you could try adding a node similar to https://www.kernel.org/doc/Documentation/devicetree/bindings/fpga/altera-hps2fpga-bridge.txt into https://github.com/altera-fpga/linux-socfpga/blob/QPDS25.1_REL_GSRD_PR/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts, but with another values for register range, reset, and clock. You will also need a custom driver to access the node you created.117Views0likes7CommentsRe: Operating system kernel-level FPGA bridge communication
Can you try running "bridge enable" in the U-boot Shell? You may refer to https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-7/f-series/soc/boot-examples/ug-linux-boot-agx7-soc/#enabling-bridges-from-u-boot (the same method works for Agilex5)149Views1like1Comment