AlanCLTan
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Re: Arria 10 SoC – USB devices always enumerating as Full-Speed (Yocto 4.1, dwc2)
Hi angelsz15 Arria 10 SoC FPGA does not contain an integrated High‑Speed USB PHY. You will need to provide an external USB2.0 HS PHY. Could you check are these defined in the device tree?: phy_type = "ulpi"; dr_mode = "host"; phys = <&usb_phy0>; phy-names = "usb2-phy"; snps,phyif = <0>; // ULPI snps,hs_phy_type = "ulpi"; snps,fs_phy_type = "dedicated"; Also, check for the PHY binding status: dmesg | grep -i phy dmesg | grep -i ulpi -Alan10Views0likes0CommentsRe: Cyclone5 SoC: U-Boot not detecting USB-HUB
Hi teiram I was checking back your usb0 node definition. usb0: usb@ffb00000 { compatible = "snps,dwc2"; reg = <0xffb00000 0xffff>; interrupts = <0 125 4>; clocks = <&usb_mp_clk>; clock-names = "otg"; resets = <&rst USB0_RESET>; reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; }; Could you set the status to "okay"? Also, included a few things to try, i.e. increasing the reg size. &usb0 { compatible = "snps,dwc2"; reg = <0xffb00000 0x10000>; /* increase the size */ /* Verify the correct interrupt for your platform */ interrupts = <0 125 4>; clocks = <&usb_mp_clk>; clock-names = "otg"; resets = <&rst USB0_RESET>; reset-names = "dwc2"; /* ensure this matches your reset controller driver */ /* Key properties for ULPI host */ dr_mode = "host"; snps,phy_type = "ulpi"; /* helps older/newer drivers */ phys = <&usbphy0>; phy-names = "usb2-phy"; snps,dis_u2_susphy_quirk; /* common with external ULPI PHYs */ /* Power for the port */ vbus-supply = <&vbus_5v>; /* Pinctrl must be applied */ pinctrl-names = "default"; pinctrl-0 = <&usb0_ulpi_pins>; status = "okay"; }; As for the vbus_5v and usb0_ulpi_pins definitions, you could refer to this: vbus_5v: regulator-vbus-5v { compatible = "regulator-fixed"; regulator-name = "vbus-5v"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpioX Y GPIO_ACTIVE_HIGH>; /* Replace with your actual GPIO controlling the VBUS switch (if any) */ enable-active-high; regulator-always-on; /* or remove and let runtime handle it */ status = "okay"; }; &pinctrl { usb0_ulpi_pins: usb0-ulpi-pins { pins = "..."; /* Replace with your platform’s exact pin/function descriptors */ function = "usb"; bias-disable; drive-strength = <8>; slew-rate = <1>; }; }; Regards, Alan0Views0likes1CommentRe: Cyclone5 SoC: U-Boot not detecting USB-HUB
Hi teiram , Welcome back! phys instead of usb-phy -- From my study, "phys" is for modern controller and "usb-phys" is used for older controller. Not 100% sure on the impact but please experiment with both cases :) As for the CONFIG_*s, they should be found in Linux's kernel menu-config. Thanks38Views0likes3CommentsRe: Cyclone5 SoC: U-Boot not detecting USB-HUB
Hi teiram, Let's try these: 1. Do you have a PHY node for USB3300 in the your previous working u-boot? Something like the example below. Add it into the dtsi: { /* Define the PHY node outside the soc bus */ usb_phy0: usb-phy { compatible = "usb-nop-xceiv"; #phy-cells = <0>; reset-gpios = <&portb 0 GPIO_ACTIVE_LOW>; status = "okay"; }; }; &usb1 { status = "okay"; dr_mode = "host"; // Usually 'host' for Cyclone V boards usb-phy = <&usb_phy0>; // Link to the PHY node }; 2. Make sure the Linux kconfig options (set in defconfig) are set: CONFIG_USB_DWC2=y CONFIG_USB_OHCI_HCD=y --- sometimes needed for full/low speed support CONFIG_PHY=y CONFIG_NOP_USB_XCEIV=y --- Essential if using the usb-nop-xceiv compatible string. CONFIG_USB_ULPI=y --- Required for the ULPI interface protocol. 3. The USB3300 or an downstream hub requires specific GPIO states to be enabled before the USB stack starts. You can do this in U-Boot with: gpio set 9 usb start17Views0likes0CommentsRe: Cyclone V: how to enable USB1 with a ULPI USB PHY (USB3320)?
Hi dpeng, Let me understand further on your setup: CPEN routed to a VBUS power switch enable (active‑high) RESET# of the USB3320 driven by HPS_GPIO0 (active‑low) Is that correct? Could you confirm the checklist below: Confirm the 5 V input to the VBUS power switch is present. Verify the switch enable pin is active-high and connected to CPEN directly. Verify the reference clock to USP3320 (26MHz) is present and stable. Scope the ULPI CLK pin from the PHY (usually 60 MHz output to the MAC). Also check that ULPI I/O voltage rails (1.8 V or 3.3 V) are correct. For OTG micro‑AB, ID grounded: A‑device (host); ID floating: B‑device (peripheral). If the ID pin is floating, the PHY may not try to source VBUS. Best regards, Alan48Views0likes0CommentsRe: Cyclone V: how to boot Linux from QSPI?
Hi dpeng The latest 25.1std release for Cyclone V is now available. Please visit https://altera-fpga.github.io/rel-25.1/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/#2-cyclone-v-soc-boot-from-qspi for the way to boot from QSPI. Thanks, Alan45Views0likes0Comments