KarelSterckx
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Re: Syntax error in initial block
The error messages for each line within the initial block are: Error (10170): Verilog HDL syntax error at dsb.v(10) near text: . Check for and fix any syntax errors that appear immediately before or at the specified keyword. Error (10170): Verilog HDL syntax error at dsb.v(10) near text: " "; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. Code before the initial block is: module dsb (clk_c, plc_lsb, plc_usb, dsb); input clk_c; output plc_lsb, plc_usb, dsb; reg [3:0] div, lpc, pa; // div = counter used to obtain clk_m from clk_c wire [3:0]sub, add; reg [7:0] plc_lsb, plc_usb; reg [8:0] dsb; initial begin div = 4’b0; lpc = 4’b0; pa = 4’b0; plc_lsb = 8’b0; plc_usb = 8’b0; dsb = 9’b0; end3.6KViews0likes0CommentsSyntax error in initial block
I am using Quartus Prime Lite Edition v22.1.1 In my Verilog HDL code, I include the following initial block: initial begin div = 4’b0; lpc = 4’b0; pa = 4’b0; plc_lsb = 8’b0; plc_usb = 8’b0; dsb = 9’b0; end A syntax error in every line of the initial block is generated when I compile the code. I do not see anything wrong with the code though.Solved3.6KViews0likes6Comments