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How to connect 32bit master to 8GB ddr memory using Qsys interconnect.
I'm using a board with Agilex FPGA and 8 GB DDR4 memory. I'm trying to connect a 32bit AXI master (a soft cpu core) to DDR controller in Platform Designer. The Platform Designer interconnect automatically adds AXI-Avalon interface conversion. But I have trouble wiht DDR address range since it requires more than 32 bits to be fully addressed. Since the master address space is only 32 bit it can't address above 4GB. Is there any way to edit the address map in order to make only the first 2GB of DDR accessible to the master?. In the address map editor I can modify only the base address of slaves, including DDR memory controller. I could not find any way to set the top address or the address range, the top address is being automatically derived from DDR controller as 8G and is not editable. So I get a connectivity error. Error: core.Rocket_core_0.mem_axi4_master: dram0_0.ctrl_amm_0 (0x0..0x3ffffffff) is outside the master's address range (0x0..0xffffffff) How to modify the address range in order to limit DDR access within 0x00000000 -0x80000000? In Vivado the address map editor allows to define not only the base address but also the address range of each slave item. How the same result can be achieved in Platform Designer?Solved2.5KViews0likes4CommentsSynthesis crashes on Quartus Pro
I get crash while synthesizing a vhdl design on Quartus Pro for Stratix and Agilex FPGAs The design elaborates without any problem. Here is the crash log Tried on Quartus Pro 22.1(Windows), 22.2(Linux), 22.3(Linux) Problem Details Error: *** Fatal Error: Segment Violation: faulting address=0x18, PC=0x7f1996928e1a : 0x7f1996928e1a: synth_vrfx2!Map::GetItem(void const*) const + 0x10 Module: quartus_syn Stack Trace: Err Handler 0x136a4: ERR_UNWINDER_BACKTRACE::get_stack_trace(void const**, int, int, void*) + 0xe0 (ccl_err) Err Handler 0x91d6c: msg_ie_get_call_stack(void*) + 0xc4 (ccl_msg) Err Handler 0x93cd2: MSG_INTERNAL_ERROR::report_fatal(char const*, void*, bool) + 0x40 (ccl_msg) Err Handler 0x170b1: err_report_fatal_exception(char const*, void*, bool) + 0x60 (ccl_err) Err Handler 0x17351: err_sigaction_handler + 0x191 (ccl_err) System 0x42520: (c) Quartus 0xdcbe1a: Map::GetItem(void const*) const + 0x10 (synth_vrfx2) Quartus 0xdcbff1: Map::GetValue(void const*) const + 0x9 (synth_vrfx2) Quartus 0xc667ad: VhdlLibrary::GetPrimUnit(char const*, unsigned int, unsigned int) const + 0x3b (synth_vrfx2) Quartus 0x7d4896: new_verific::vrfx2_get_expected_parameters_vhdl(char const*, char const*, std::vector<VhdlIdDef*, std::allocator<VhdlIdDef*> >&, BASEX_ELABORATE_INFO*) + 0x47 (synth_vrfx2) Quartus 0x7e108a: new_verific::vrfx2_get_modules_units_and_params(char const*, std::vector<BASEX_ENTITY*, std::allocator<BASEX_ENTITY*> > const&, BASEX_ELABORATE_INFO*, new_verific::VRFX2_ANALYZER*, bool, VeriModule**, VhdlPrimaryUnit**, Array*, Array*, Map*, std::vector<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > >*, std::vector<VhdlIdDef*, std::allocator<VhdlIdDef*> >*) + 0x2aa (synth_vrfx2) Quartus 0x7e21a6: new_verific::VRFX2_EXTRACTOR::extract_hierarchy(char const*, std::vector<BASEX_ENTITY*, std::allocator<BASEX_ENTITY*> > const&, BASEX_ELABORATE_INFO*, bool, bool, bool, bool) + 0xc7a (synth_vrfx2) Quartus 0xfafe1: QIS_RTL_STAGE::IMPL::elaborate_verific(QHD_PARTITION*, BASEX_ENTITY*, BASEX_ELAB_INFO_CORE&, std::vector<BASEX_ENTITY*, std::allocator<BASEX_ENTITY*> > const&) + 0x327 (synth_qis) Quartus 0x10af86: QIS_RTL_STAGE::IMPL::elaborate(QHD_PARTITION&) + 0x20b4 (synth_qis) Quartus 0x271b2a: SYNTH::QIS::SYNTHESIS_FLOW::process_new_components() + 0x9e6 (synth_qis) Quartus 0x2736cb: SYNTH::QIS::SYNTHESIS_FLOW::high_level_synthesis() + 0x625 (synth_qis) Quartus 0x273b44: SYNTH::QIS::SYNTHESIS_FLOW::run_current_phase() + 0x34a (synth_qis) Quartus 0x2741d5: SYNTH::QIS::SYNTHESIS_FLOW::run_full_flow(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, bool, bool) + 0x43b (synth_qis) Quartus 0x171df5: QIS_RTL_STAGE::IMPL::synthesize(QHD_PARTITION&, bool, bool) + 0x5d5 (synth_qis) Quartus 0x1720ee: QIS_RTL_STAGE::synthesize(QHD_PARTITION&, bool, bool) + 0x12 (synth_qis) Quartus 0xb6a32: qis_synthesize + 0x241 (synth_qis) Quartus 0x4c942: TclNRRunCallbacks + 0x42 (tcl8.6) Quartus 0x4de7b: TclEvalEx + 0x68b (tcl8.6) Quartus 0xf3f0e: Tcl_FSEvalFileEx + 0x25e (tcl8.6) Quartus 0xf3ffe: Tcl_EvalFile + 0x2e (tcl8.6) Quartus 0x2a8fb: qexe_evaluate_tcl_script(std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&) + 0x3de (comp_qexe) Quartus 0x2dd72: qexe_do_tcl(QEXE_FRAMEWORK*, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::list<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > > const&, bool, bool) + 0x4c2 (comp_qexe) Quartus 0x2ee7a: qexe_run_tcl_option(QEXE_FRAMEWORK*, char const*, std::__cxx11::list<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > >*, bool) + 0x66e (comp_qexe) Quartus 0x5e294: QCU::DETAIL::intialise_qhd_and_run_qexe(QCU_FRAMEWORK&, FIO_PATH const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const&, char const*, std::__cxx11::list<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > >*, bool) + 0x99 (comp_qcu) Quartus 0x5e66e: qcu_run_tcl_option(QCU_FRAMEWORK*, char const*, std::__cxx11::list<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > >*, bool) + 0x343 (comp_qcu) Quartus 0x40909b: qsyn2_tcl_process_default_flow_option(ACF_VARIABLE_TYPE_ENUM, char const*) + 0x501 (quartus_syn) Quartus 0x3421c: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0xba2 (comp_qexe) Quartus 0x408a5b: qsyn2_main(int, char const**) + 0x139 (quartus_syn) Quartus 0x4e886: msg_main_thread(void*) + 0x10 (ccl_msg) Quartus 0x4faa4: msg_thread_wrapper(void* (*)(void*), void*) + 0x8c (ccl_msg) Quartus 0x1f468: mem_thread_wrapper(void* (*)(void*), void*) + 0x98 (ccl_mem) Quartus 0x10f3a: err_thread_wrapper(void* (*)(void*), void*) + 0x1e (ccl_err) Quartus 0xb7f5: thr_thread_wrapper + 0x15 (ccl_thr) Quartus 0x4f9c4: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xd8 (ccl_msg) Quartus 0x408b93: main + 0x26 (quartus_syn) System 0x29d90: (c) System 0x29e40: __libc_start_main + 0x80 (c) Quartus 0x408879: _start + 0x29 (quartus_syn) End-trace Executable: qpro Comment: None System Information Platform: linux64 OS name: Ubuntu 22.04.1 OS version: 22 Quartus Prime Information Address bits: 64 Version: 22.3.0 Build: 104 Edition: Pro EditionSolved1.9KViews0likes8CommentsHow to create IP from a multy-library vhdl project in Quartus.
I have a Quartus vhdl project consisting of about 10 vhdl libraries and about 150 vhdl files. Would like to create an IP from it in order to instantiate to a bigger design. The same project for xilinx FPGAs is being easily encapsulated into IP by "Create and package IP" command in Vivado . Could not find an similar functionality with Qsys/Platform Designer (e.g. to read the project qpf file instead of manually specifying all the files). And could not find a way to group files in libraries while adding them to Qsys project. The library pragma is not supported since it is Quartus Pro Is there any practical way to do it?Solved844Views0likes2CommentsHow to create IP from a multy-library vhdl project in Quartus.
I have a Quartus vhdl project consisting of about 10 vhdl libraries and about 150 vhdl files. Would like to create an IP from it in order to instantiate to a bigger design. The same project for xilinx FPGAs is being easily encapsulated into IP by "Create and package IP" command in Vivado . Could not find an similar functionality with Qsys/Platform designer (e.g. to read the project qpf file instead of manually specifying all the files). And could not find a way to group files in libraries while adding them to Qsys project. The library pragma is not supported since it is Quartus Pro Is there any practical way to do it?Solved1.3KViews0likes4Comments