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Re: Agilex5 - Timings configuration
I’m glad that your question has been addressed, I now transition this thread to community support. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you.10Views0likes0CommentsRe: Agilex 5 RSU, application image addition fails
Hi, Thanks for the screenshots. The rsu_status output shows: failing code: 0xF0030003 which means major error 0xF003 = BITSTREAM_CORRUPTION, with a minor code 0x0003. This is why it is not listed in the “Mailbox RSU Error Code Responses” table, because it is a different status format (major and minor), and the minor part is often not user defined. Refer: RSU Status and Error Codes & RSU Error Code Responses first failing image address: 0x0048C000 confirms the failure is on the newly added image. Most common causes for this scenario: 1. Wrong .rpd content - Please confirm RemoteImage_jic.rpd is an application image .rpd generated from the application .sof only, not an .rpd generated from the initial .jic flash image flow. The “add application image” procedure expects an application-only .rpd. Refer: Adding an Application Image & Generating an Application Image - If you use rsu1.tcl/program_flash, generate the .rpd with Bit swap = Off because the script already handles the byte ordering. 2. Erase alignment / overlap - Ensure the new image start address 0x0048C000 is aligned to your flash erase granularity, and that programming the new image does not erase a larger block that overlaps the end of the existing P1 image. Refer: Modifying the List of Application Images & Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image Next actions we recommend: - Regenerate an application-only .rpd from the application .sof (Bit swap Off if using rsu1.tcl), then reprogram at an erase-aligned address, update both CPB0 and CPB1 pointers, and retry. Refer: Generating an Application Image & Adding an Application Image If you share (a) how RemoteImage_jic.rpd was generated and (b) your QSPI flash part number and erase sizes, we can suggest a safe aligned start address and confirm the correct file settings. Check, Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image Regards, Fakhrul5Views1like0CommentsRe: Cyclone I (EP1C3) Configuration Issues: Sequence and Environment Dependent Failures
Hi HKana17, Thanks for the detailed write-up. With legacy Cyclone I and older Quartus, there are many possible causes here (power, flash wear, board variation, cable/driver differences, programming settings, and more). As written, it is difficult to troubleshoot because it mixes several symptoms across different boards, dates, and environments. To keep this focused, could you please pick one failing board and one specific failure, then share only the minimum items below? Which exact file is used (SOF or POF), and the full Quartus version build string Programming method (JTAG or AS), and the exact Programmer settings used (including verify, erase, compression, and any “auto-detect” results) The board power-up sequence and whether the FPGA is configured from EPCS at power-up or only after programming What you observe on key pins if available (nSTATUS, CONF_DONE, nCONFIG), or any LEDs tied to them A repeatable step list: start condition, program steps, power cycle or not, and expected vs actual behavior Without a repeatable single-case report, the best anyone can do is guess. If you can narrow it to one board and one reproduction path, people here can give more targeted advice. Regards, Fakhrul3Views0likes0CommentsRe: Where to find BSDL files on Altera Web?
Hi Martin, Yes, we are still working on the migration from the Intel website to the Altera website. This has also been noted in another thread: https://community.altera.com/discussions/fpga-device/agilex5-a5eb013bb23be4s-bsdl/351052 Sorry for the inconvenience. Thank you for reporting this. Regards, Fakhrul5Views0likes0CommentsRe: Agilex 7 boot from config flash over JTAG
As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Altera experts. Otherwise, community users will continue to assist you here. Thank you.15Views0likes0CommentsRe: JTAG Chain Broken on Agilex 7-I Dev Kit
Hi Serge, Thanks for your time and for completing the checks. Your unit shipped on 18 Nov 2024. The standard warranty is 1 year (ended on 18 Nov 2025), so it is now out of warranty. Because of this, we cannot proceed with an RMA replacement through support. You may try to contact your distributor or supplier to ask about repair or replacement outside warranty. For now, I will close this case on our side. Thank you for your cooperation. Regards, Fakhrul4Views0likes0CommentsRe: Generating RBF raw binary file on Max 10
I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread. Thank you.13Views0likes0Comments