FakhrulA_altera
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Re: MAX10 nCONFIG pin slew rate requirement
Hi FrankK, I'm glad that your issue is resolved. I will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Best regards, Altera Technical Support4Views0likes0CommentsRe: MAX10 nCONFIG pin slew rate requirement
Hi FrankK, To answer your question, Altera does not publish a slew‑rate spec for nCONFIG in the MAX 10 datasheet. Refer MAX 10 FPGA Device Datasheet During configuration, MAX 10 uses Schmitt‑trigger input buffers by default, so slow or noisy edges are tolerated. MAX 10 FPGA Signal Integrity Design Guidelines Schmitt input hysteresis is about 180 mV at 3.3 V, 150 mV at 2.5 V, 120 mV at 1.8 V, 110 mV at 1.5 V. Check here https://docs.altera.com/r/docs/683794/current/max-10-fpga-device-datasheet/hysteresis-specifications-for-schmitt-trigger-input To force reconfiguration, keep nCONFIG low at least 2 µs. https://community.altera.com/kb/knowledge-base/what-are-the-minimum-nconfig-low-pulse-width-and-the-maximum-nstatus-low-pulse-w/347246 Connect nCONFIG high on power‑up, typically with a 10 kΩ pull‑up to VCCIO. Refer MAX 10 FPGA Device Family Pin Connection Guidelines Holding nCONFIG low to delay configuration does not relax the POR ramp‑time requirements. Try refer Possibility to avoid configuration power requirements for single-supply MAX10 by using nconfig In practice, use a clean, monotonic nCONFIG edge and keep noise away from the threshold region. The Schmitt buffer helps, but clean edges are still best. MAX 10 FPGA Signal Integrity Design Guidelines Regards, Fakhrul8Views1like2CommentsRe: Agilex 7 R-Tile RBES FPGA – Board Fails to Power On and JTAG Not Detected
Hi nskim, There are no new updates. As noted earlier, the unit is out of warranty, so we cannot proceed with an RMA. Based on the troubleshooting already done, the device likely has a hardware fault. If recovery is still needed, please arrange a paid repair through your distributor. At this point, I’ll transition this thread to community support. If you have any new questions, feel free to open a new thread to receive assistance from Altera experts. Otherwise, the community members will continue to help you here. Thank you for your engagement! Best regards, Fakhrul0Views0likes0CommentsRe: Hard reset with USB-Blaster and Quartus
Hi Alkesh, A hard reset shouldn’t be required. This usually happens because the JTAG TAP or a device is left in a test state. Between scans, reset the TAP, park all devices in BYPASS, return to Run‑Test/Idle, and do a short DR flush. Avoid ending in EXTEST or HIGHZ. If your device is Stratix 10, enable boundary‑scan once via the MISCCTRL instruction. Quartus Programmer isn’t a full boundary‑scan tester, so you need to manage these states or use a dedicated BST tool. Reference: Intel MAX 10 JTAG Boundary‑Scan Testing User Guide Intel® MAX® 10 JTAG Boundary-Scan Testing User Guide What device you are using btw? Regards, Fakhrul6Views0likes0CommentsRe: Agilex 7 R-Tile RBES FPGA – Board Fails to Power On and JTAG Not Detected
Hi nskim, Thanks for your patience while we checked with our internal team. We’ve confirmed the unit is out of warranty, so we’re unable to proceed with an RMA. Based on the extensive troubleshooting, the device appears to have a hardware fault. If recovery is still needed, please proceed with a paid repair via your distributor (if applicable). Regards, Fakhrul0Views0likes1CommentRe: Estimate the power consumption of the MAX 10 device 10M08SLV81I7G
Hi Hachiware, We are checking with our internal team on this. Thank you for your patience. Many colleagues were out of office over the year-end and New Year, which caused a delay. We will update you as soon as we have the status. Regards, Fakhrul2Views0likes0CommentsRe: Agilex 7 R-Tile RBES FPGA – Board Fails to Power On and JTAG Not Detected
Hi nskim, We are checking with our internal team on the Devkit warranty. Thank you for your patience. Many colleagues were out of office over the year-end and New Year, which caused a delay. We will update you as soon as we have the status. Regards, Fakhrul15Views0likes1CommentRe: nSTATUS is sometimes asserted low during Agilex-F configuration when operating in PMBus slave mode
Hi, I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Fakhrul3Views0likes0CommentsRe: Requesting you to resolve the programming on Cyclone V SX SoC Development Kit
As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Intel experts. Otherwise, community users will continue to assist you here. Thank you.2Views0likes0Comments