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FakhrulA_altera
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Re: USB-Blaster II malfunction
Hi Frank, Thank you for the detailed test results. Since programming succeeds with quartus_pgm, the USB-Blaster II, programming file, and JTAG chain appear functional. The issue is likely related to the Programmer GUI/JTAG server state, combined with the 24 MHz JTAG frequency. Please try the following: Continue using 6 MHz with automatic clock adjustment disabled. Close the Programmer, restart the JTAG server, and reconnect the USB-Blaster II. Connect the cable directly to the PC and temporarily disconnect other USB-UART or FTDI devices. Ensure the USB-Blaster II driver comes from the Quartus Prime Standard Edition 25.1 installation and that drivers from different releases are not mixed. You may continue using quartus_pgm as a temporary workaround. References: Changing the USB-Blaster II Clock Frequency USB-Blaster II Recovery After Hardware Setup Regards, Fakhrul8Views0likes0CommentsRe: Cyclone 4 PS Configuration Timing Parameters
Hi Christophe, I'm glad you were able to find a solution. I will now transition this thread to community support. The information shared here will serve as a useful reference for other community members who encounter a similar issue in the future. Thank you for sharing the outcome. Regards, Fakhrul40Views0likes0CommentsRe: Workaround for TCK frq. limitations on USB-Blaster I/II/III & Clones (fixing "JTAG chain broken")
Hi Jan, Thank you for sharing this information and for disclosing your affiliation. Please note that the official USB-Blaster II supports TCK rates from 10 kHz to 6 MHz using 24/n settings, in addition to 6, 16, and 24 MHz. USB-Blaster III also supports adjustable TCK and frequency auto-adjustment. Therefore, the stated frequency limitations are not accurate. As this post primarily promotes a third-party commercial product, we are unable to endorse it and will close the thread. Thank you for your understanding. Relevant references: FPGA Download Cable II User Guide USB-Blaster III TCK adjustment USB-Blaster III auto-adjust Regards, Fakhrul14Views0likes0CommentsRe: MT25QL128 Not Available in ALTASMI_PARALLEL Configuration Device List
Hi Umesh, Thank you for confirming that MT25QL128 works with the EPCQ128/EPCQ128A setting. For AS multi-device configuration, no separate VHDL or IP is normally required. Set the master to AS mode and the slave to PS mode, with nCONFIG, nSTATUS, and CONF_DONE shared, and route DATA[0] and DCLK to the slave as described in the Cyclone 10 LP handbook. Please note that nCONFIG is an input, not a handshake output from the slave. Please also verify the DCLK timing: start DCLK only after nSTATUS is high, and provide at least two additional falling DCLK edges after CONF_DONE rises. If necessary, enable a post-chain bitstream padding byte. If the issue remains, please share one waveform showing nCONFIG, nSTATUS, CONF_DONE, DCLK, and DATA[0], together with the exact FPGA part numbers and Quartus version. Best regards, Fakhrul4Views1like0CommentsRe: MT25Q512 Programming Issue When Connected to Cyclone 10CX150Y
Hi Aviram, Thank you for the clarification. TRI_STATE_SPI_PINS OFF affects the AS/QSPI pins only while the FPGA is in user mode. A Quartus Erase operation erases the flash but does not immediately clear the FPGA’s SRAM configuration. For external programming, please assert nCONFIG low and nCE high before any QSPI activity and keep them asserted through Erase/Program/Verify. With nCONFIG low, the Cyclone 10 GX loses its configuration and tri-states its I/O, so the assignment is no longer active. As the next diagnostic step, please power-cycle both devices while holding nCONFIG low, then reset/initialize the MT25Q512, including addressing, QE and protection settings, before programming. If the issue remains, please provide QSPI waveforms and the exact flash suffix and programmer version. Regards, Fakhrul4Views0likes0CommentsRe: EPM7064LI44-15 – Xeltek SuperPro 610P Program OK but Verify fails at address 0x50
Hello Kalyan, Thank you for the details. The log shows “ID checks error. Ignore.” before programming and verification. Therefore, “Program OK” does not confirm successful programming; the device ID or programming algorithm does not match the detected device. Please: Do not ignore the ID-check error. Run Xeltek’s insertion/contact test and confirm device orientation. Update the SuperPro software, firmware, and device library. Ask Xeltek to confirm that the selected EPM7064@PLCC44 algorithm and SA244 adapter explicitly support EPM7064LI44-15. If the mismatch remains, please provide Xeltek with the detected/expected ID values (A7/0F), algorithm date, and verify failure at 0x50. Since this is a third-party programmer algorithm issue, Xeltek is best positioned to provide the corrected algorithm. Thank you. Fakhrul3Views0likes0CommentsRe: Quartus 25.1std | Signal Tap Crash
Hi Ryan, Thank you for the details and the crash log. The stack points to a Signal Tap acquisition-path failure (sld_chi / construct_load_data) when Run Analysis starts. A few quick checks should help isolate this: Please confirm compile, program, and Signal Tap are all done in Quartus Prime 25.1 Standard (avoid mixing with 21.1 SOF/tools). If Power-Up Trigger is enabled, please disable it, recompile, reprogram, and try Run Analysis again. As dandanlau suggested: remove the current .stp, run Project → Clean Project, create a new STP with 1–2 simple signals and a valid acquisition clock, then retest. Regarding Windows 11 vs “Windows 10” in the log: Quartus often reports Windows 10 on Windows 11 systems; that alone is not the cause. If it still crashes with a fresh minimal STP (Power-Up Trigger off), please share: Whether Power-Up Trigger was used Cyclone V OPN / cable type Project archive (.qar) including .stp and the crash report Best regards, Fakhrul6Views0likes0CommentsRe: Preconfiguration BSDL Editor for Agilex 7 with disabled F-Tiles
Hi Rob, Thank you for your patience. I have confirmed that the same issue is being handled through Altera Premier Support (APS), where a revised BSDL with the 12B/13B sections removed has been supplied for validation. Its syntax and scan length still need checking against your board. As this issue is already being investigated through the related APS case, I will close this forum thread to avoid duplicate tracking. This closure applies only to the forum discussion; the technical investigation continues through APS. Thank you for your understanding. Regards, Fakhrul7Views0likes0CommentsRe: About EPCQ-L device
Hi MinzhiWang, Thank you for your question. Yes, a 256-Mb flash has enough capacity for the 10CX220. According to the Cyclone 10 GX Device Datasheet (Table 54, Configuration Bit Stream Sizes), every Cyclone 10 GX density, including the 10CX105 and 10CX220, has the same estimated uncompressed configuration bitstream size of 91,729,632 bits. The datasheet recommends a 256-Mb or higher-density configuration device for all of them. Since MT25QU256 already works for your 10CX105 design, it has enough capacity for a single 10CX220 configuration image. Please note: If you plan to store multiple images, such as a factory and an application image for Remote System Upgrade, add up the size of each image to confirm the total still fits. Please check the actual .rbf or .jic size generated by Quartus Prime for your 10CX220 design, as the datasheet values are estimates. Reference: docs.altera.com/r/docs/683828/current/c…heet/configuration-files Since this thread was opened by another user for a different question, could you please post any follow-up questions in a new thread? This helps us track your request and give you a focused response. Best regards, Fakhrul2Views0likes0Comments