FakhrulA_altera
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Re: Cyclone VGT Dev Kit boards - some new boards failing to boot from NOR Flash
Hi GordWait, Thank you for the additional findings and the serial numbers. We would like to clarify a couple of points to ensure we correctly understand the latest results. In an earlier update, you mentioned that the factory max5.pof was able to boot the marginal boards, whereas your custom build did not. In the latest update, you noted that some boards do not boot reliably even with the factory image. Could you please help confirm: For SN 5CPCIE00100119, 5CPCIE00100129, and 5CPCIE00100262, what is the behavior when using the unmodified factory max5.pof? Always boots Boots intermittently Never boots For each of the above boards, could you share the MAX V timing report from the corresponding build that was programmed onto the board? In particular, the recovery/setup timing around the critical clk_config path that you identified earlier. This will help us determine whether the latest observations are still consistent with the timing-margin hypothesis or indicate a different issue. Thanks.8Views0likes1CommentRe: JTAG pins order for USB Blaster III - 1.27" header
Hi Zvi, Yes. For a new board with the USB Blaster III 1.27 mm, 2 × 5 JTAG connector, use the USB Blaster III micro-header pinout, not the older 2.54 mm header order. For JTAG mode, the pinout is: Pin Signal 1 - VCC_TARGET 2 - TMS 3 - GND 4 - TCK 5 - Not connected 6 - TDO 7 - Not connected 8 - TDI 9 - GND 10 - nPROCRST So, pin 7 is not used for JTAG. It is used as nCS only in Active Serial mode. The 1.27 mm connector was introduced for a smaller cable interface. The included adapter board maps this new pinout to the older 2.54 mm header, which is why the signal order differs from older cables. For a direct connection, use a keyed 1.27 mm, 2 × 5 male header on the target board and follow the pin numbering shown in the USB Blaster III User Guide. At this time, the adapter-board mapping in the user guide is the available reference for this interface. USB Blaster III FPGA Development Cable User Guide Regards, Fakhrul0Views0likes0CommentsRe: Brand new USB-BLASTER 3 issues
Hi Sruk, Thank you for confirming that you are using the adapter and the legacy 2.54 mm pinout. The known USB-Blaster III Product ID issue affects Active Serial programming only. It should not prevent normal JTAG device detection. Related KDB: Why Can't I Program Using Active Serial Programming with my USB Blaster III? For this JTAG error, please check the target voltage reference at the connector. USB-Blaster III uses the target board VREF to set its JTAG signal levels. Measure VREF at the adapter/header while the board is powered. It must be within the supported range and match the FPGA JTAG I/O voltage. Try Lowering the JTAG Clock Speed. You can try reducing the JTAG clock speed using: jtagconfig --setparam <cable_number> JtagClock 6M Also, please confirm: The target board is fully powered before scanning. TDO is not held high by another device or circuit. No other JTAG source is connected to the chain. The cable LED state and the output from jtagconfig. Since the same boards work with an older cable, if VREF and TDO are correct, this may indicate a cable issue. The "Engineering Sample" marking on the box is unusual for a production unit purchased through DigiKey. It would be worth confirming with DigiKey whether this is expected for your order. Thanks, Fakhrul1View0likes0CommentsRe: Understanding the Purpose of Active Discharge Circuits in FPGA Power Design (Terasic DE10 Reference)
Hi sovad, Just checking if there is any update from your side. As Frank mentioned, some FPGA families such as Cyclone 10 GX, Arria 10, and Agilex may have specific power sequencing or power-down requirements. In some designs, an active discharge circuit can help meet these requirements by discharging the power rails faster. For the Terasic DE10 board, the exact reason depends on the specific schematic and Terasic’s board-level design. Please check with Terasic if you need confirmation on their implementation. Since there has been no further response, we will consider this thread closed. If you have any further questions, please feel free to post a new update.28Views0likes0CommentsRe: Error (209014): CONF_DONE pin failed to go high in device 1.
Hi Sameer, Apologies for the delayed response. Could you please refer to the following KDB articles for this specific CONF_DONE error? https://community.altera.com/kb/knowledge-base/why-do-i-receive-the-error-conf-done-pin-failed-to-go-high-in-device-x-when-i-tr/347292 https://community.altera.com/kb/knowledge-base/error-conf-done-pin-failed-to-go-high-in-device-/340233 Please also try programming with the attached .sof file and confirm whether the same error is observed. For the next step, could you please try the following? Keep all DIP switches at the factory default setting. Remove any external connection or daughter card from the board. Power cycle the board. Program only the official example .sof file from the Cyclone V E Development Kit design package. If probing is available, please check the CONF_DONE, nSTATUS, and nCONFIG signal levels during programming. Also, could you confirm how many Cyclone V E development kit boards show this same behavior out of the total boards tested? Regards, Fakhrul4Views0likes1CommentRe: Regarding Cyclone 10 LP AS Configuration Timing Parameters
Hi mario, Thank you for your question. For Cyclone 10 LP AS configuration mode, the public datasheet only specifies the AS DCLK frequency range. The documented DCLK range is 20 MHz to 40 MHz, with 33 MHz typical. Cyclone® 10 LP Device Datasheet The specific timing items below are not separately specified in the Cyclone 10 LP datasheet: DCLK high time and low time minimum values Delay from DCLK edge to ASDO data change Time from nCSO Low to the first DCLK edge Time from the last DCLK edge to nCSO High Because these values are not published, we cannot provide guaranteed min/max timing numbers for them. For Flash ROM selection, please make sure the Flash device can support the Cyclone 10 LP AS DCLK frequency range, especially the maximum 40 MHz operating point. If your design requires guaranteed detailed pin timing, we recommend verifying this on the actual board or raising a formal support request for further review. Best regards, Fakhrul6Views0likes0CommentsRe: Max 10 Device Migration from SA auf SC
Hi Jonas, For MAX 10 SA to SC migration, please do not assume full pin compatibility only because the package is the same. Some pins can have different functions between feature options, for example analog pins on SA may become power or GND pins on SC. The recommended approach is to compare the official MAX 10 pin-out file for both exact ordering part numbers and check the MAX 10 Pin Connection Guidelines for unused or dual-purpose pin handling. Altera provides MAX 10 pinout files and pin connection guidelines for this purpose. In general: Pins defined as GND or power pins for one device option must follow that device requirement. Unused dual-purpose or analog-related pins should follow the pin connection guideline. If one PCB must support both SA and SC variants, it is safer to provide board-level options such as jumper or stuffing option for pins that are different. Regards, Fakhrul15Views0likes0CommentsRe: Error (209014): CONF_DONE pin failed to go high in device 1.
Hi Sameer, Thank you for checking with the default DIP switch settings and also trying the example .sof. Since the same CONF_DONE error occurs with both your design and the official example .sof, this may not be related to your LED design. The next step is to isolate whether the issue is from the board setup or the configuration path. Please help to check the following: Confirm the exact FPGA part number printed on the board/device matches 5CEFA7F31. In Quartus Programmer, try Auto Detect again and confirm the JTAG chain is detected correctly. Make sure only the correct .sof for 5CEFA7F31 is assigned to the FPGA device. Power cycle the board, then try programming again using the built-in USB-Blaster II. If possible, please share a clear screenshot of the Quartus Programmer setup, including the full JTAG chain and assigned .sof file. As the example .sof also fails, the issue may be related to board configuration, power, or the CONF_DONE path rather than the design file itself. Regards, Fakhrul11Views0likes3CommentsRe: Understanding the Purpose of Active Discharge Circuits in FPGA Power Design (Terasic DE10 Reference)
Hi sovad, From the schematic, this looks like a power-down fast discharge circuit. When the power enable signal is turned off, the MOSFETs are enabled and the related FPGA power rails are discharged to GND through low-value resistors. The purpose is to remove remaining voltage on the rails faster after power-off. This can help avoid leftover voltage, slow power-down, quick power-cycle issues, or possible back-powering through other devices. This is mainly a board-level power design choice and is not a general mandatory requirement for all Altera FPGA designs. It depends on the power design, regulator behavior, rail capacitance, and sequencing needs. For the exact reason this was added on the Terasic DE10 board, please check with Terasic, as this is part of their board implementation.17Views0likes0Comments