FakhrulA_altera
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Re: JTAG Chain Broken on Agilex 7-I Dev Kit
Hi Serge, Thanks for the update. Could you try below: Return all switches to Default Settings. Include: SW2[1:3] = OFF/OFF/OFF (JTAG mode), SW5.1 = OFF (on‑board Download Cable), SW5.2 = OFF (FPGA in chain), SW5.3 = ON (MAX 10 JTAG enabled). If your board uses SW8 instead of SW5, use the equivalent entries in the same table. Refer: Default Settings tables. Check the D6 Power Good LED. Blue ON means all rails are good. If OFF, address power first. Refer: LEDs table. In BTS, open Power Monitor GUI and capture the rail status screenshot. Refer: “Monitor On‑board Power through Power Monitor GUI.” In Quartus Programmer, run JTAG Chain Debugger and share the integrity report if auto‑detect still fails. Intel help recommends this when the chain cannot be scanned. Perform Board Restore through Quartus Prime Programmer, then power cycle and retry JTAG. Refer: “Perform Board Restore through Quartus Prime Programmer.” You may refer to this user guide for the above steps: Agilex™ 7 FPGA I-Series Development Kit User Guide If the chain is still broken with the FPGA in the path after the above, it suggests a board‑side JTAG issue, it can indicate a board integrity problem once power and connections are confirmed. We can proceed with RMA. Please also share clear photos or a list of the current SW1–SW6/SW8 positions. Regards, FakhrulRe: JTAG Chain Broken on Agilex 7-I Dev Kit
Hi Serge93, Thanks for reporting this. Please try these quick steps: On the host, restart the JTAG server and run jtagconfig, or use the JTAG Chain Debugger to isolate the issue. Refer: JTAG error (Unexpected error in JTAG server Return the board to factory default switch settings and select the on‑board Download Cable as the JTAG source. Refer: Factory Default Switch Settings Temporarily bypass the FPGA in the JTAG chain (SW5.2 or SW8.2 by board revision), then attempt a Board Restore to recover the MAX 10 and factory image. Refer: JTAG chain broken after FPGA configuration If it still fails, try an external USB‑Blaster II and reduce the JTAG clock in Programmer. Please share your kit ordering code and the output of jtagconfig --debug after step 3. Regards, FakhrulRe: Reset offset for Cyclone 10 GX 085
As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Altera experts. Otherwise, community users will continue to assist you here. Thank you.Re: M67981 supplemental mechanical information
As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Altera experts. Otherwise, community users will continue to assist you here. Thank you.Re: Part no query-5CEFA9F31I7NFA
Hi Santoshmbca, The above reply mentioned by zhnezhonghehuan2 is correct. “FA” is an optional ordering suffix used for logistics or customer‑specific options. You can just ignore this suffix. Cyclone V status is active. It will be available until 2035. (may be extend based on demand). Regards, FakhrulRe: M67981 supplemental mechanical information
Hi benstrawbridge, Could you try check the following. I attached here for two package codes R24C & R24D for Drawing No.M67981: Intel Agilex® 7 F-Series Device Allegro* PCB Footprint for R24D (2340D) Package - PRELIMINARY Intel Agilex® 7 F-Series Device Allegro* PCB Footprint for R24C (2340A) Package - PRELIMINARYRe: Reset offset for Cyclone 10 GX 085
Hi tato, You’re seeing two separate issues: BSP @ 0x02000000 fails because Nios V requires the reset vector to be exactly the base of the chosen reset memory region (your GSFI avl_mem base not equal to 0x02000000). Refer :5.10. Summary of Nios V Processor Vector Configuration and BSP Settings JIC packaging @ 0x02000000 fails because the first 32 bytes there are reserved (Option Bits), so app.hex starting at 0x02000000 may overlaps. Could you try: If GSFI base is 0x01000000, start HEX at 0x01000000. Refer :5.10. Summary of Nios V Processor Vector Configuration and BSP Settings If you must use 0x02000000, start HEX at 0x02000020 to avoid the Option Bits area. Verify with the generated .map and avoid HEX overlap errors. Refer: 2.3.1.4.3. Defining Address Span Extender Linker Memory Device Also, make sure GSFI parameters match your flash and configuration mode. Refer: Nios® V Boot Option Regards, Fakhrul
