FFULC
New ContributorJoined 7 years ago
User Profile
New Contributor
User Widgets
Contributions
Re: Cannot detect MAX V cpld and Cyclonne 5GX in the same jtag chain
Hi @ak6dn I have isolated the MAXV in the chain and still no luck 😞 I would like to send the cards back to the board assembler and get the part changed but they have no stock - long lead time issues everywhere ! Perhaps I'll send it back anyway and get them to remove, recheck the central gnd pad connection and then reflow the same device. But is there anything else that I can try first ? I have read that 2nd hand parts already programmed may have the jtag interface disabled but the supplier is adamant that the parts are brand new. Is there anything else that causes an inactive TDO ? ThanksRe: Cannot detect MAX V cpld and Cyclonne 5GX in the same jtag chain
Hi @ak6dn I have just put a scope probe on the jtag pins of the MAXV, see attached. The first two pictures attached show the TCK (ch1) and TMS (ch2) during testing the jtag chain. The clock looks pretty good, this was a concern. Third picture shows TCK and TDI - does the device latch data on the rising edge of TCK ? Fourth picture shows TCK and TDO So I never see any activity on the TDO output pin from the MAXV but when I test the JTAG chain in the Quartus Chain Debugger it still manages to detect the downstream 5CGX. How does it do this when the TDO line that feeds in to the TDI pin of the Cyclone has no activity on it ? I have also checked all the VCC pins and all look good.Re: Cannot detect MAX V cpld and Cyclonne 5GX in the same jtag chain
Hi @ak6dn Yes if I bypass the MAXV I can successfully program the FPGA, I'll need to modify the board to isolate the MAXV. I'll look at that next. One thing to mention is that I am using MAXV40ZE64 on the MAXV80ZE64 footprint, I presume there are no pin differences ? Also I have DEV_CLRn and DEV_OEn floating is this an issue? Also all unused IO are floatingCannot detect MAX V cpld and Cyclonne 5GX in the same jtag chain
Hi I have a new circuit card design with a Byte Blaster 10 pin header connected via jtag to a MAX 5M40ZE64 and then a Cyclone 5CGXFC5C6. The Quartus programmer cannot detect the chain. When I run jtag diagnotics it detects the Cyclone (2nd device) but says the TMS or TCK are grounded at the first part (unidentified). When I put the scope prob on the TMS and TCK CPLD pins I see activity. If I bypass the MAXV (by shorting TDI to TDO pins at the MAXV) I can program the Cyclone. Is there something in my setup that is wrong and causing the CPLD to remain undetected ? Another thing worth pointing out is that the schematic is drawn for a 5M80ZE64I5N but the part fitted on the cards is a 5M40ZE64A5N. Is there any differences in pin out? Thanks FrankRe: PCIe Hard IP core in Cyclone V GX
Hi John I have shown you the screenshot before but can I use REFCLK1 as an alternative PCIe clk? REF_CLK comes on to our board through a backplane from the Root Complex. If we have signal integrity issues then I'd like to connect a local 100Mhz LVDS clock to REFCLK1. Will this work? Thanks FrankRe: PCIe Hard IP core in Cyclone V GX
Hi John I plan to use a MAX 5M80ZE64 alongside my Cyclone V GX. The pinout spreadsheet for the E64 package has excluded the GND or NC pins. Can I make an assumption that all the missing pins are all GNDs? All the other package types seem to include the GND pins Thanks Frank
