giulio2
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Maximum bandwidth intel Arria 10gx, Strattix 10 sx
Hello everyone, What is the maximum bandwidth that intel Arria 10 gx and intel Strattix 10 sx can arrive to write and load from global memory? I have searched many places for the answer to this question but could not find it. From the report in View->System Viewer I can see that the throughput for Arria is 960 Mb/s and for Strattix is 1400 Mb/s. Are these the maximum bandwidth for these devices? Thank you in advance.946Views0likes3CommentsRe: [FPGA USM]Issue in implementing zero-copy data transfer
Hello, Thanks for your answer, I was trying trying to adapt the zero-copy mechanism in my implementation of the hash join (in order to reduce the total latency). I followed what is done in this tutorial, https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/DPC%2B%2BFPGA/Tutorials/DesignPatterns/zero_copy_data_transfer. In my project I have included, as they are, the implementations of "unroller", "streaming data" and "tuple" that are present in your github repository. https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/DPC%2B%2BFPGA/ReferenceDesigns/db/src/db_utils As I said before if I compile for the FPGA emulator it works and provide correct results. When I have to compile for hardware, I target in my CMake "intel_s10sx_pac:pac_s10_usm" as FPGA board, then I select a Strattix node through devcloud_login command, and submit the compilation job. The compilation goes fine and I am also to generate the report. To run the binary, I do the following: -I select a Strattix node in an interactive way(using devcloud_login command) -I run "aocl initialize acl0 pac_s10_usm" -I run the binary ( here in runtime gets stuck) By getting stuck, I mean it never produces the final results (same behavior when doing an infinite loop). I tried to compile and run your zero-copy data transfer code(https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/DPC%2B%2BFPGA/Tutorials/DesignPatterns/zero_copy_data_transfer) and it worked (it runs entirely). So I just don't understand what I'm doing wrong. Thank you in advance for your availability.1.5KViews0likes1Comment[FPGA USM]Issue in implementing zero-copy data transfer
Hello everyone, I'm trying to reproduce the zero-copy data transfer mechanism for a personal project. The code compiles and runs on FPGA Emulator, so now I'm trying to compile and run on FPGA hardware with USM support(intel_s10sx_pac:pac_s10_usm) in devcloud. The compilation goes fine, but when I have to run it gets stuck, this is strange to me since in FPGA Emulator it entirely runs and reproduces correct results, so I guess I am missing something about how to run code written for FPGA with usm support. What I do is the following: through devcloud_login I select an available strattix node, then I run: aocl initialize acl0 pac_s10_usm and finally I run the binary. I'm also uploading a zip of the code containing the kernels. Thank you in advance for your availability.1.6KViews0likes5Comments- 1KViews0likes0Comments
FPGA Build fail on Devcloud
Hello, I'm trying to compile a project on FPGA Hardware on Devcloud. following these steps: qsub -I -l nodes=1:fpga_compile:ppn=2 -l walltime=24:00:00 source /opt/intel/inteloneapi/setvars.sh mkdir build cd build cmake .. make fpga I'm targeting intel_s10sx_pac:pac_s10 this is the output of the compilation: Scanning dependencies of target onesql [ 33%] Linking CXX static library ../libonesql.a [ 33%] Built target onesql Scanning dependencies of target main_fpga.fpga [ 66%] Building CXX object CMakeFiles/main_fpga.fpga.dir/main_fpga.cpp.o [100%] Linking CXX executable main_fpga.fpga Killed Error: Optimizer FAILED. Refer to /home/u145208/tmp/main_fpga-757e3b-527f59/main_fpga_757e3b_527f59.log for details. llvm-foreach: dpcpp: error: fpga compiler command failed with exit code 1 (use -v to see invocation) make[3]: *** [CMakeFiles/main_fpga.fpga.dir/build.make:85: main_fpga.fpga] Error 1 make[2]: *** [CMakeFiles/Makefile2:124: CMakeFiles/main_fpga.fpga.dir/all] Error 2 make[1]: *** [CMakeFiles/Makefile2:104: CMakeFiles/fpga.dir/rule] Error 2 make: *** [Makefile:118: fpga] Error 2 this is the content of the main_fpga_757e3b_527f59.log file Compiler Command: aoc -o /home/u145208/tmp/main_fpga-757e3b-527f59.aocx /home/u145208/tmp/main_fpga-42dab2-90b297.spv -sycl -dep-files=/home/u145208/tmp/main_fpga.cpp-325514.d -output-report-folder=main_fpga.fpga.prj -g -hardware -parallel=2 -seed=2 -board=intel_s10sx_pac:pac_s10 Killed The project compile and run on FPGA Emulator and I'm also able to build the report. Anyone seeing this error or know hot to fix it? Thank you in advance.1.9KViews0likes6Comments