Daire_C_Intel
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Can you assign 'altera_reserved' JTAG pins to JTAG interface inside user logic?
I'm working off a max10 dev kit for now but will be soon scaling up for a larger design. All boards seem to have a JTAG dongle interface but you can't assign these pins to your own logic as they are reserved. I've instantiated a 3rd party processor IP core which includes a JTAG interface for debug. I'd like to route this core's JTAG signals to the board's JTAG dongle header, for use with 3rd party debug software, but direct access using the pin planner isn't allowed. Is there a way around this?1.7KViews0likes2CommentsQuartus is not recognising the Stratix 10 chip on my Stratix 10 development kit.
While using the programmer to program a design onto my Stratix 10 via USB-Blaster, the JTAG chain picks up the Max V on the board and picks up the Stratix 10 as an unknown device with JTAG ID 032250DD. This ID is within the pgm_parts.txt file in the Quartus directory under a lot of products. I've tried lots of things but still can't program the board.3.9KViews0likes4Comments