User Profile
Saikiranbelana
New ContributorJoined 4 years ago
User Widgets
Contributions
Re: OpenCL bitstream unsigning crashes - Arria 10 PAC Card
Hi @hareesh , Please find the attached zip file for vector addition that using for compilation using Inteldevstack. We are using Arria 10 PAC Card. The compilation takes a long time and is successful but while unsigning the `aocx` file, the terminal session crashes with the error: Error: Module: openssl.py, Function: __init__, Line: 332 Failed to find crypto library (libcrypto.so). please can you suggest a solution to fix the error? Regards, Saikiran Belana2.7KViews0likes0CommentsRe: OpenCL bitstream unsigning crashes - Arria 10 PAC Card
Hi Hareesh, here's my log for OpenSSL and libcrypto fpga@fpgaserver2:~$ cat /etc/ld.so.conf.d/mylib.conf /usr/lib/x86_64-linux-gnu/libcrypto.so.1.1 fpga@fpgaserver2:~$ ldconfig -p | grep libcrypto libcrypto.so.1.1 (libc6,x86-64) => /usr/lib/x86_64-linux-gnu/libcrypto.so.1.1 libcrypto.so.1.0.0 (libc6,x86-64) => /usr/lib/x86_64-linux-gnu/libcrypto.so.1.0.0 libcrypto.so (libc6,x86-64) => /usr/lib/x86_64-linux-gnu/libcrypto.so fpga@fpgaserver2:~$ openssl version OpenSSL 1.1.1 11 Sep 2018 I have installed `libssl-dev` package and configured `ldconfig`. Thanks & Regards, Saikiran Belana2.7KViews0likes0CommentsOpenCL bitstream unsigning crashes - Arria 10 PAC Card
Hi, I was trying to unsign the compiled aocx file. It crashes by this error: fpga@fpgaserver2:~/A10_OPENCL/vector_add/bin$ source /home/fpga/inteldevstack/a10_gx_pac_ias_1_2_1_pv/opencl/opencl_bsp/linux64/libexec/sign_aocx.sh -H openssl_manager -i vector_add.aocx -r NULL -k NULL -o vector_add_unsigned.aocx The script assumes the PACsign and Intel Acceleration Stack environment is setup. If not run the command : <stack_installation_path>/init_env.sh hsm_manager=openssl_manager aocx filename/path=vector_add.aocx root_public_key=NULL csk_public_key=NULL output filename/path=vector_add_unsigned.aocx null=1 openssl hsm_manager_options=openssl_manager input path =. input filename =vector_add.aocx output path =. output filename =vector_add_unsigned.aocx Extracted the filename as vector_add_unsigned 1. Extracted the bin from the aocx 2. Extracted the gzip compressed GBS file from the .bin gzip: temp_vector_add_unsigned.gbs already exists; do you wish to overwrite (y or n)? y 3. Uncompressed .gz it to get the GBS file Initiating PACSign tool to sign the GBS. This process will take a couple of minutes... Creating unsigned aocx file by signing a NULL key No root key specified. Generate unsigned bitstream? Y = yes, N = no: Y No CSK specified. Generate unsigned bitstream? Y = yes, N = no: Y No root entry hash bitstream specified. Verification will not be done. Continue? Y = yes, N = no: Y Error: Module: openssl.py, Function: __init__, Line: 332 Failed to find crypto library (libcrypto.so). For RedHat-based distros, install package openssl-devel. For Debian-based distros, install package libssl-dev. I have installed `libssl-dev` and it still causes the same error. I have edited ldconfig to add `libcrypto.so` library too. Is there something I'm missing with openssl installation ? @Arria10 @fpga @intel2.8KViews0likes10CommentsRe: Intel Devstack-OpenCL unable to detect PAC Cards
Here's the output for `lspci -vv | grep acce`: server2@ubuntu:~$ sudo lspci -vv | grep acce af:00.0 Processing accelerators: Intel Corporation Device 09c4 for `lspci -vv` : af:00.0 Processing accelerators: Intel Corporation Device 09c4 Subsystem: Intel Corporation Device 0000 Physical Slot: 5 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 39 NUMA node: 1 Region 0: Memory at dbffff00000 (64-bit, prefetchable) [size=512K] Region 2: Memory at dbfffe00000 (64-bit, prefetchable) [size=1M] Capabilities: [68] MSI-X: Enable+ Count=7 Masked- Vector table: BAR=0 offset=00009000 PBA: BAR=0 offset=0000a000 Capabilities: [78] Power Management version 3 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- Capabilities: [80] Express (v2) Endpoint, MSI 00 DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0.000W DevCtl: Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+ RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset- MaxPayload 256 bytes, MaxReadReq 4096 bytes DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 8GT/s, Width x8, ASPM not supported, Exit Latency L0s <4us, L1 <1us ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- DevCap2: Completion Timeout: Range B, TimeoutDis-, LTR-, OBFF Not Supported DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis- Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- Compliance De-emphasis: -6dB LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+, EqualizationPhase1+ EqualizationPhase2+, EqualizationPhase3+, LinkEqualizationRequest- Capabilities: [100 v2] Advanced Error Reporting UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- UESvrt: DLP- SDES+ TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr- CEMsk: RxErr+ BadTLP+ BadDLLP+ Rollover+ Timeout+ NonFatalErr+ AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn- Capabilities: [160 v1] Alternative Routing-ID Interpretation (ARI) ARICap: MFVC- ACS-, Next Function: 0 ARICtl: MFVC- ACS-, Function Group: 0 Capabilities: [200 v1] Single Root I/O Virtualization (SR-IOV) IOVCap: Migration-, Interrupt Message Number: 000 IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+ IOVSta: Migration- Initial VFs: 1, Total VFs: 1, Number of VFs: 0, Function Dependency Link: 00 VF offset: 1, stride: 1, Device ID: 09c5 Supported Page Size: 00000553, System Page Size: 00000001 Region 0: Memory at 00000dbfffd00000 (64-bit, prefetchable) Region 4: Memory at 00000dbffff80000 (64-bit, prefetchable) VF Migration: offset: 00000000, BIR: 0 Capabilities: [280 v1] #19 Kernel driver in use: intel-fpga-pci Kernel modules: intel_fpga_pci2.9KViews0likes0CommentsRe: FPGA plugin integration with Slrum Workload Manager
Will OPAE APIs be sufficient to manage multi-FPGAs resources? We are dealing with HPC clusters in this case. By any chance, can we use OneAPI for integrating the Arria 10 FPGAs as plugins to HPC Schedulers like Slurm(the same way as OpenPBS implemented in DevCloud? Thanks, Saikiran2.7KViews0likes0CommentsRe: Intel Devstack-OpenCL unable to detect PAC Cards
Hi @JohnT_Intel , Here's the output for lspci server2@ubuntu:~$ lspci | grep acce af:00.0 Processing accelerators: Intel Corporation Device 09c4 The FPGA is still available and only shows with lspci and fpgainfo. I think the problem is with the drivers. When I move the FPGA to a different system, It works there.3KViews0likes0Comments