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Dan18
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NewBe: Qesta Intel starter edition -- unable to checkout a license
Hello, Using Quartus lite I create a simple schematic diagram -- and and2 gate with two inputs and output, mapped to the cyclon l10 pins. I then wanted to simulate the schematic -- however, upon starting the simulator i got a licensing error: c:/intelfpga_lite/21.1/questa_fse/win64//vsim -c -do MKRVIDOR4000.do Unable to checkout a license. Make sure your license file environment variable (e.g., LM_LICENSE_FILE) is set correctly and then run 'lmutil lmdiag' to diagnose the problem. Unable to checkout a license. Vsim is closing. I am unsure what to do, since I installed the free questa product any help is much appreciated, Dan892Views0likes2CommentsRe: Newbe Question: Quartus lite -- installing new ip (for audrino Vidor)
Thank you for your reply. The error message i got was that the system PLL was not found. I later found for the Vidor board a system_pll ip files (system_pll.ppf, system_pll.qip, system_pll.v) on a git and simply copied those files into the working directory of the project. This worked to get the error disappear. thanks, Dan1KViews1like1CommentNewbe Question: Quartus lite -- installing new ip (for audrino Vidor)
Hello, I am using Quartus lite to work with the Audrino Vidor which includes a Cyclone 10 FPGA and am trying to get a sample project working [1]. After compiling i get an error that one of the IPs referenced isn't known and that it needs to be added to the path. I found a number of IPs for the Audrino i got from a github, and saved in a local folder, but can't figure out how to add these to the known IPs. I noticed some global and local path settings for IP, but adding the folder in both of them doesn't recognize them. Any guidance to get them added is much appreciated. thank you, Dan [1] https://www.arduino.cc/en/Tutorial/VidorQuartusVHDL1.1KViews0likes3CommentsRe: Newbe question ... how to integrate an FPGA based logic cirucit with a C/C++ program on posix
Thank you for your response. I am surely going to deep dive into OpenCL to figure out what can be done with it ... From what I read, and if i understood this correctly, it seems that OpenCL is an alternative to hardware description languages such as Verilog. Encoded OpenCL calls are implemented in FPGA, while appearing to the developer as specialized C/C++ library functions. I guess, I had a different kind of "architecture" in mind -- a way to to create an own FPGA "circuit" -- using, for example, Verilog, and then to have a way to memory map the FPGA to a CPU memory on a standard PC. Perhaps those acceleration cards are close to what i had in mind ... thank you, Dan1.1KViews0likes0CommentsNewbe question ... how to integrate an FPGA based logic cirucit with a C/C++ program on posix
Hello, I am trying to get my head around FPGAs and in particular how i could accelerate a C/C++ programs by having some calls have an FPGA compute results. Ideally, i would want to have some kind of shared memory space whereby an in-memory data structure in C/C++ is accessible via FPGA logic and vice-versa, where some resulting logic is accessible by the C/C++ program -- all the while communication between the CPU based C++ program and the FPGA card is high speed -- essentially via memory access bandwidth. Can this be done? IS there some tutorial about this that i could review? thank you, Dan1.2KViews0likes4Comments