rhe
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Re: Timing Constraint for modules
As I said in my first post, I develop modules that can be used in many projects where clock relationship can be different. Sometimes they can be synchronous and sometines not. That's why I need to put a set false path to be more general. Moreover, if clocks are effectively synchronous, indeed I don't need a set_false path ... but i don't need a synchronizer neither ... so I won't use this synchronizer module.... (If I know that clocks are synchronous by design) Well, my question was not about the need or not of a timing constraint but how to find a specific register based on a module name. And if i had already found some scripts to do that I wouldn't ask the question here. So if you know where I can find these script I will be grateful. best regards2.8KViews0likes1CommentRe: Timing Constraint for modules
I disagree with you on this specific example. My module is here to cross clock domain, whatever the clock are synchronous or not. If clock are asynchronous, by setting clock as asynchronous in my SDC it will of course disable any timing constraint between these 2 clock domains. If clock are synchronous ... yes by constraining source clock and destination clock, all path will be constrained including the input of the synchronizer. But, it could be very difficult to meet the timing due to clock frequencies and phase relation ship. This is the reason why I want to add a set false path at the input of the synchronizer as it is recommended by everyone. The reason why I want to put a max delay between the 2 FlipFlop is to deal with metastability that will occur on first flip flop since input can be totally asynchronous to destination clock (It can be pushbutton for example ...). By setting a maxdelay between the 2 FFs, it will "force" to place the 2 FFs relatively close one of each other : and this will reduce metastability probability. One more time, my question is more global than this example. I try to find a solution to constrain any module which needs a specific constraint quite automatically like quartus does it when creating some ip core like LVDS_SERDES IP core on Cyclone10 Gx. Here find attach the 2 files that quartus create which constrains any instantiation of this module in the design. TCL file include some generic function that will find modules and targets elements SDC file will call this tcl file apply specific constraint to some element in each module instantiation. I try to modify these file for my project but I do not succeed ... Note : I had to change file extension to import files in this forum because it doesn't allow TCL file and SDC files ....2.9KViews0likes3CommentsTiming Constraint for modules
Hello, I designed some basic modules I reuse in all my project. For instance, I have a synchronization module I called "resync_module" which is a 2 flip-flop synchronizer that I use when I need to use 1 signal from one clock domain to another clock domain. My question is about timing constraint, SDC file and probably TCL file. I want to specify some constraints on this "resync_module". First I would like to set a false path to any signal going into first flip-flop, and then a max delay between first flip-flop to second equal to 80% of clock period. BUT, I do not want to manually specify this constraints to all instances of this modules in my project. I would like to write a SDC (and TCL) file that will search for all instance of my module named "resync_module" and then create for each instance the correct constraint to apply (because for each instance, clock frequency can be different so constraint must also be different). Can someone help me to write this functionnality for quartus ? Thanks a lot. Sebastien2.9KViews0likes8Comments