Ali8
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OneAPI: FPGA simulation fails when using USM
Hello, I have been trying the different OneAPI tutorial examples for FPGAs. I can run all the examples with FPGA emulation. However, FPGA simulation only works for examples that do not use USM or buffers (simulation works fine when using host pipes!). When I try to run FPGA simulation for the vector_add example with USM, I get the following error message: Assertion failed: *fd != nullptr && "IPCSharedMemoryMaster() failed to open file!", file src/acl_msim_mem_manager.cpp, line 185 I am using OneAPI version 24.1, Intel Quartus Pro 23.4 and Questa starter edition 23.3. I am using “Arria10” as a target when compiling for simulation. Thanks,HLS System of Tasks: Task Reuse
Hello, The following code snippet is from one of the System of Tasks examples provided with Intel hls. From my understanding, compiling this will creates three copies of the same task’s hardware pipelined with internal streams in between for communication. I am interested in implementing a similar structure using system of tasks but with hundreds of pipelined instances of the same task. Is there a way to implement something like this efficiently? I understand that it is not possible to use streams with arrays! Thanks,Simultaneous read and write to the same memory address using HLS
Hello, I have a specific need to be able to perform a simultaneous read and write to the same memory address in a dual-port RAM with the output of the RAM showing the newly written data. According to this post, this is possible in RTL: What happens when I perform a simultaneous read and write to the same address in dual-port RAM? (intel.com). Clearly, this is a memory dependency in HLS that will cause the compiler to increase the initiation interval. As I am new to intel HLS, I don’t understand how the ivdep pragma works and I am not sure if it can actually be used to force a simultaneous read and write to the same address. Is this something possible in HLS? Thanks,
