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Slave Memory in OneAPI HLS Flow
In intel HLS compiler, we can implement a slave memory inside a component using hls_avalon_slave_memory_argument(N). The slave memory can also be implemented with M20K embedded RAM and can have the same architectural optimizations as all other internal component memories (such as banking or coalescing). With slave memory, a master can access the memory without a component invocation. I want to implement a slave memory within a kernel using OneAPI HLS flow. Can you direct me to a OneAPI example code that uses slave memories.Solved1.1KViews0likes4CommentsOneAPI: FPGA simulation fails when using USM
Hello, I have been trying the different OneAPI tutorial examples for FPGAs. I can run all the examples with FPGA emulation. However, FPGA simulation only works for examples that do not use USM or buffers (simulation works fine when using host pipes!). When I try to run FPGA simulation for the vector_add example with USM, I get the following error message: Assertion failed: *fd != nullptr && "IPCSharedMemoryMaster() failed to open file!", file src/acl_msim_mem_manager.cpp, line 185 I am using OneAPI version 24.1, Intel Quartus Pro 23.4 and Questa starter edition 23.3. I am using “Arria10” as a target when compiling for simulation. Thanks,1.3KViews0likes4CommentsOneAPI and FPGA SoCs
With the Intel FPGA SDK for OpenCL, it is possible to target FPGA SoCs with board support packages (host code on the Arm hard processor and kernel on FPGA fabric). Is this something that is going to be supported with OneAPI/Sycl in the near future?Solved1.5KViews0likes2CommentsHLS System of Tasks: Task Reuse
Hello, The following code snippet is from one of the System of Tasks examples provided with Intel hls. From my understanding, compiling this will creates three copies of the same task’s hardware pipelined with internal streams in between for communication. I am interested in implementing a similar structure using system of tasks but with hundreds of pipelined instances of the same task. Is there a way to implement something like this efficiently? I understand that it is not possible to use streams with arrays! Thanks,1.6KViews0likes4CommentsSimultaneous read and write to the same memory address using HLS
Hello, I have a specific need to be able to perform a simultaneous read and write to the same memory address in a dual-port RAM with the output of the RAM showing the newly written data. According to this post, this is possible in RTL: What happens when I perform a simultaneous read and write to the same address in dual-port RAM? (intel.com). Clearly, this is a memory dependency in HLS that will cause the compiler to increase the initiation interval. As I am new to intel HLS, I don’t understand how the ivdep pragma works and I am not sure if it can actually be used to force a simultaneous read and write to the same address. Is this something possible in HLS? Thanks,2.5KViews0likes3Comments