khyam
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Re: How to parameterize the single on-chip memory with different slave interfaces
On-chip RAM IP support the dual port RAM enable option, so we can have two slave interface, but in my design I am looking for more than two slave interfaces, Is it possible to parameterize On-chip RAM IP with more than two slave interfaces.1.2KViews0likes0CommentsHow to parameterize the single on-chip memory with different slave interfaces
Hi, I am designing the SoC using Quartus pro 19.2 of the platform designer tool. In this design, four different IPs are used to build the complete SoC. Three master module IPs and one slave module IP, here slave IP is On-Chip Memory(RAM or ROM) Intel FPGA IP. So three master modules communicate with single slave On-Chip memory, it has a memory bottleneck, each clock cycle only one request will be processed. To hence the throughput of memory, to instantiated another On-Chip Memory(RAM or ROM) Intel FPGA IP, in this situation two slave interface and three master interface, each clock cycle two request will be processed. The On-Chip Memory(RAM or ROM) Intel FPGA IP has the option to parameterize memory type(RAM or ROM) and size(16, 32, 64, 128-bits). I want to know that, instead of instantiating the two memory block IPs to create two slave interfaces, can I use single Memory IP to parameterize the slave interface (based on memory depth, for example, 0-1023 depth will access one slave interface and 1024 to 511 depth will access another slave interface in Single Memory IP instead two memory IPs instantiating ). Any way depth and width are parameterized in memory IP, is it possible to parameterize slave interface for single memory IP. I looked into the IP edit parameters tab, I didn't find any option to parameterize the slave interface. Please let me know if you have any input. Thank you in advance for your time and consideration.1.3KViews0likes3CommentsRe: Remote debug AFU on-chip memory using System Console.
Hello @RichardTanSY_Altera , I am able to launch and connect AFU through remote debug and I have done debugging of AFU using signal tap tool. Instead of signal tap, we can use the system console for FPGA memory debug using Avalon MM commands like master_write_32 and master_read_32. I tried using the system console tool for FPGA memory debugging, the claim command used for claiming the master service for operation(FPGA memory read/write). I got the below error for claiming master service. error: claim_service: Could not claim service at /devices/1/(link)/TCP/sld_hub_controller_system_0_fabric.h2t_0/sld_hub/(110:132 v1 #0)/phy_0/master: Channel(s) have already been claimed, and the new claims are not compatible with the existing claims(s).2.1KViews0likes2CommentsAFU design with On-chip memory, How to debug on-chip memory of AFU design using system console
Hi all, Remote debugging is necessary when you cannot access the JTAG connections. So the application running on Intel PAC card is debug using remote debugging with system console over TCP/IP. Use of signal tap we are able to debug our design, it's working fine. To debug the on-chip memory using the system console, the design should have Avalon JTAG master IP instance, then we can use the system console master service to debug when FPGA connected using JATAG or USB blaster cable. Here we debugging the design using the system console over TCP/IP, to access the system console master service, which masters service we need to access JTAG master service, processor master service, or TCP master. we are accessing Avalon JTAG master service, we got an error message this master service is already claimed. When I am accessing the TCP master service, so I claim the master service. But unable to read and write data to On-chip memory. I have a question, is it necessary to have an ethernet IP/MAC IP instance in our design, So it will help for accessing/connecting on-chip memory, like Avalon master IP instance for JTAG or USB cable. Or we can use Avalon master IP instance to access on-chip memory over TCP/IP using system console. Please help me1.1KViews0likes1CommentRemote debug AFU on-chip memory using System Console.
Hi, I have designed AFU with on-chip memory. I am doing remote debug of AFU using mmlink, system console, and signal tap. I want to read and write the on-chip memory using the system console(remote method, that is TCP, the SLD hub controller). I am using the following command to communicate on-chip memory using the system console. 1) cmd: get_service_paths device rsp: /devices/1 2) cmd: set m_path [lindex [get_service_paths master] 0 ] rsp: /devices/1/(link)/TCP/sld_hub_controller_system_0_fabric.h2t_0/sld_hub/(110:132 v1 #0)/phy_0/master 3) cmd: set c_path [claim_service master $m_path ""] rsp: error: claim_service: Could not claim service at /devices/1/(link)/TCP/sld_hub_controller_system_0_fabric.h2t_0/sld_hub/(110:132 v1 #0)/phy_0/master: Channel(s) have already been claimed, and the new claims are not compatible with the existing claims(s). while executing "claim_service master $m_path """ invoked from within "set c_path [claim_service master $m_path ""]" I got the above error when using the claim_service command to claims the service for exclusive use. Even for the open_service command also I am getting the same error. Could you please provide the solution to the above issue?2.2KViews0likes5CommentsRe: Alt_sld_fab_0.alt_sld_fab_0: add_instance: Can't create component type altera_sld_agent_endpoint_tie
Solution: Add below command to the afu.qsf file to set stp file set_global_assignment -name VERILOG_MACRO "INCLUDE_REMOTE_STP" then run the design using $run.sh command or Add this line to filelist.txt file. +define+INCLUDE_REMOTE_STP Then build the design using following command afu_synth_setup --source filelist.txt build/stp So, It will add signal tap host instance in the design.5KViews0likes0CommentsRe: Alt_sld_fab_0.alt_sld_fab_0: add_instance: Can't create component type altera_sld_agent_endpoint_tie
I used sample example nlb_mode_0_stp, its has signal tap file(.stp). I used mmlink utility of OPAE2.0 for debugging the Arria 10 GX and D5005 PAC card with system console and quartus signal tap tool. The AFU with .stp file compiled successfully and I can see the signal tap instance but receive the following error when trying to acquire data. "Error (261005): can't find the instance. Download a design with SRAM Object File Containing this instance." When I used my own design, that is integrated with Xeon host processor in OPAE Platform. without Signal tap (.stp) file, it compiled successfully, but when i try to add .stp file instance in my design, I am getting below error. Error (11176): Alt_sld_fab_0.alt_sld_fab_0: add_instance: Can't create component type altera_sld_agent_endpoint_tieoff Yup looked the post you provide, but he didn't explained, how he resolve the issue.5.1KViews0likes1CommentAlt_sld_fab_0.alt_sld_fab_0: add_instance: Can't create component type altera_sld_agent_endpoint_tie
Arria 10 GX FPGA Error (11176): Alt_sld_fab_0.alt_sld_fab_0: add_instance: Can't create component type altera_sld_agent_endpoint_tieoff Info (11172): invoked from within Info (11172): "add_instance sldfabric_t0 altera_sld_agent_endpoint_tieoff" Info (11172): ("eval" body line 32) Info (11172): invoked from within Info (11172): "eval $tcl" Info (11172): (procedure "compose" line 36) Info (11172): invoked from within Info (11172): "compose" Info (11172): invoked from within Info (11172): "interp eval $slave { Info (11172): Compose Info (11172): }" Error (11176): Alt_sld_fab_0.alt_sld_fab_0.alt_sld_fab_0.auto_signaltap_add_afu.clock: auto_signaltap_add_afu.clock must be connected to a clock output Info (11172): *************************************************************** Info (11172): *************************************************************** Error (11176): Error opening ../../../build/qdb/_compiler/afu_default/_flat/19.2.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0.ip.Solved5.1KViews0likes8Comments