robertzab
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Re: Agilex 5 - PCIe
Hi, When I initially saw in your documentation that there was information about changing the BIOS setting from “AUTO” to the appropriate standard, I changed it immediately, but unfortunately I got the same error. Unfortunately, I’ve had a problem with the DevKit (MK-A5E065BB32AES1) right from the start—I even started a thread on the forum about it: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Problem-DevKit-Agilex-5-MK-A5E065BB32AES1/m-p/1675889#M29564 And from the Arrow distributor, I received their startup kit: https://www.arrow.com/en/research-and-events/articles/new-intel-arrow-axe5-eagle-fpga-dev-kit-discover-the-molex-interconnects I’m currently working on that one. I’ll try to check it on a different host as well. By the way, do you have any Windows drivers?Re: Agilex 5 - PCIe
Thank you for your response. I’ve reviewed the documents and followed everything according to the documentation. As I mentioned in my previous message – the system sees the device and has theoretically negotiated the link. Below is also a screenshot from SignalTap: I'm also including the "Event Counter" tab from the console: To be honest, I’m not sure where the issue is.Re: Agilex 5 - PCIe
Hi, Thank you for your response. I downloaded your project and ran it on my device. I connected the Dev-Kit to the motherboard, uploaded the program, but unfortunately, Windows does not detect any device – the same issue occurs on Linux, no device is detected. I also have a devkit from Arrow (Arrow AXE5-Eagle FPGA Dev Kit). Using the same project – only changing the pin assignments – Windows detected the connected device, and so did Linux. According to the documentation (GTS AXI Streaming Intel® FPGA IP for PCI Express Design Example User Guide), I installed the driver: I ran the test program: ./software/user/example – and got the following results: Even when performing individual read and write operations, the result is the same. From the Ubuntu side, I checked: robert@robert-Z590:~$ lspci -d 1172: 02:00.0 Unassigned class [ff00]: Altera Corporation Device 0000 (rev 01) LnkCap: Port #1, Speed 8GT/s, Width x4, ASPM L0s L1, Exit Latency L0s unlimited, L1 unlimited ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ LnkSta: Speed 8GT/s (ok), Width x4 (ok) TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- So the link between the device and the computer exists – but there is still a problem with reading and writing. I checked the signal assignments according to the documentation (GTS AXI Streaming Intel® FPGA IP for PCI Express User Guide) – all pins match the values from the table. I enabled the debug toolkit and got the following results: Do you have any idea where the issue or error might be?Re: Agilex 5 - PCIe
Hi, Thanks a lot for the info and help. It turned out the issue was on Quartus’ or Windows’ side – I solved the problem last night. Specifically, on a clean Windows installation, I installed Quartus 24.3.1, and synthesis completed successfully without any errors. So I started looking for the issue on my PC. Since we have different projects, we also use different versions of Quartus, namely 13.0, 18.1, 21, 22, and the latest 24. I checked the Windows PATH, and it pointed to the newest version. However, I began removing older versions from the system one by one, and only after removing version 21 did the synthesis finally go through correctly in version 24.3.1. Apparently, some references were assigned to a path they shouldn’t have been. The main thing is that the problem is solved. Thanks again for your help!Agilex 5 - PCIe
I have a Devkit - MK-A5E065BB32AES1. I downloaded the examples from the following link: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-modular.html I ran the pcie_ed project and opened Platform Designer to generate the code. During this process, I get the following error: Error: pcie_ed_pcie_gts_0: set_instance_parameter_value: No parameter sm_hssi_pcie_ctl_x4_ecrc_strip_hwtcl I didn’t change anything in the project. I also created a new project and added the “GTS AXI Streaming Intel FPGA IP for PCI Express” IP core, and I’m getting the same error there as well. How can I fix this, and what does this error refer to? Quartus - 24.3.1Re: Problem DevKit Agilex 5 - MK-A5E065BB32AES1
Hello, I received a new module from the distributor. However, after powering it on and running the diagnostic test (board_test_system), I’m still getting a message that two devices are not responding—see the picture below. But since I’m not going to use those devices for my project, I moved on to connecting the Texas ADC (ADC3669) through the FMC connector. That’s where I encountered another issue: the pins PIN_BH62 and PIN_BH59, which are set up as a differential pair, aren’t functioning properly as inputs/outputs—they’re not configuring correctly. I created a simple program for data collection and added a SignalTap instance, using the converter’s signal as the trigger clock. Here is what I tested: I set PIN_BH62 and PIN_BH59 as a differential output—drove them with a PLL clock and checked the oscilloscope. Result: they showed a constant high level. I set PIN_BH62 and PIN_BH59 as a differential input—applied a clock signal and observed them in SignalTap. Result: they remained high. I disconnected the converter from the FMC connector—according to SignalTap, the pins then read low. I reconnected the converter to the FMC connector—set PIN_BH62 as a single-ended input and PIN_BH59 as an output. On the converter side, I tied them together with a resistor. Observing SignalTap while driving the output high or low showed that the input correctly followed the output state. I rerouted the clock on the converter to one of the data lines and checked the waveform. This change allowed me to see the clock in SignalTap. In summary: what could be the reasons why PIN_BH62 and PIN_BH59, when configured as a differential pair, are not configuring correctly?
