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CycloneFA
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Re: Generic Serial Flash Interface IP Problem: In BSP Editor the Linker Memory Region for flash Missing
Hi. I have found the problem and solution, see: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/embedded/2020/severe--cpu--cpu--reset-memory--qspiflashavlmem--has-no-matching.html Quoted from above link: " SEVERE: CPU "cpu" reset memory "qspi_flash_avl_mem" has no matching memory region Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.1 and earlier versions, you may see below errors when creating a new NiosII® software project if NiosII®’s reset vector is set to a Generic Serial Flash Interface IP： SEVERE: CPU "cpu" reset memory "qspi_flash_avl_mem" has no matching memory region. WARNING: Tcl script "bsp-set-defaults.tcl " error: CPU "cpu" reset memory "qspi_flash_avl_mem" has no matching memory region. SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]" SEVERE: [Error]altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]" SEVERE: nios2-bsp-create-settings failed. Workaround/Fix This problem has been fixed in the Intel® Quartus® Prime Pro Edition version 20.3."4.7KViews0likes1CommentGeneric Serial Flash Interface IP Problem: In BSP Editor the Linker Memory Region for flash Missing
In my Design I use the Cyclone 10GX 10CX105YF780E5G FPGA together with the Micron MT25QU512ABB1EW9 Flash chip. I want to use the Intel Generic Serial Flash Interface in my design to be able to access the flash from within the NIOS II C Code. I Downloaded the Design example (Generic Serial Flash Interface and Nios II booting ), changed the FPGA from Cyclone5 to 10GX 10CX105YF780E5G and upgraded all the platform designer components to the Quartus Prime Pro Edition 19.1(The version I am Currently using). I also imported the design examples Nios Project and bsp project. But I did not change any further settings. The NIOS II Processor Reset Vector is still located under the intel_generic_serial_flash_interface_top_0.avl_mem with a offset of 0x00f00000 (Reset Vector Absolute adress = 0x2f00000). The Generic Serial Flash Interface IP's Control Register:(under hidden parameters) is still 0x00000101. Before generating hdl in the platform designer, I opened the bsp editor (witch opened the generic_flash_access.sopcinfo file that came with the design example). Under the "linker script" tab there are the following Linker Memory Regions: onchip_memory2_0 0x04040020 - 0x0407FFFF onchip_memory2_0 262112 32 onchip_memory2_0_BEFORE_EXCEPTION 0x04040000 - 0x0404001F onchip_memory2_0 32 0 intel_generic_serial_flash_interface_top_0_avl_mem 0x02F00020 - 0x03FFFFFF intel_generic_serial_flash_interface_top_0_avl_mem 17825760 15728672 reset 0x02F00000 - 0x02F0001F intel_generic_serial_flash_interface_top_0_avl_mem 32 15728640 intel_generic_serial_flash_interface_top_0_avl_mem_BEFORE_RESET 0x02000000 - 0x02EFFFFF intel_generic_serial_flash_interface_top_0_avl_mem 15728640 0 But after I Generate HDL... and open the bsp editor again the following errors appear: SEVERE: .entry section mapping not created because reset memory region not located at base address: 0x2f00000 SEVERE: [Error] altera_hal_linkerx_generator: The section mapping ".entry" is missing. SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry]" Also the following Linker Memory Regions disappeared: intel_generic_serial_flash_interface_top_0_avl_mem, intel_generic_serial_flash_interface_top_0_avl_mem_BEFORE_RESET and reset. Pressing Restore Defaults... did not help. Changing the Generic Serial Flash Interface IP "Device Density" to 512, for the MT25QU512ABB1EW9 flash and regenerating hdl obviously did not fix the errors either. I think for some reason the new generated "generic_flash_access.sopcinfo" file does not have the Memory Device "Iitel_generic_serial_flash_interface_top_0_avl_mem" and then those Linker Memory Regions cannot be created. How can I fix this? When setting the NIOS II Processor Reset Vector to onchip_memory2_0 with a offset of 0x00000000 everything works and I can program the VHDL and c code with the jtag. I can read and write to the flash, everything works. But then off Corse I cannot boot from flash(Because of Reset Vector...), witch is pointless. Is Quartus Prime Pro Edition 19.1 / Cyclone10 not compatible with Generic Serial Flash Interface IP? Please help!Solved4.9KViews0likes3Comments